A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology

Stasiak, D.; Mounes-Toussi, F.; Storino, S.N.

doi:10.1109/4.953483

Search citation statements

Order By: Relevance

Paper Sections

Select...

Simulation Framework1

B Limitation Of the Previous Solutions For The Floating-bod1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2004

2015

Publication Types

Select...

Article3

Other3

Relationship

Self Cite0

Independent6

Authors

Journals

Cited by 11 publications

(2 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…On the other hand, Wide fan-in gates are conventionally implemented using the multiple-stage gates in the literature [11,26]. For example, a 64-input OR gate can be designed using four 16-input OR gates connected to a 4-bit OR gate in the standard footless domino circuit (SFLD).…”

Section: Simulation Frameworkmentioning

confidence: 99%

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

Asyaei

2015

Integration, the VLSI Journal

View full text Add to dashboard Cite

Section: Simulation Frameworkmentioning

confidence: 99%

A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

Asyaei

2015

Integration, the VLSI Journal

View full text Add to dashboard Cite

“…Among the techniques, the "internal node predischarging" and the "input reordering" techniques have been widely used [11]. The internal node of DCVSL XOR, however, cannot be predischarged because of the short circuit current.…”

Section: B Limitation Of the Previous Solutions For The Floating-bodmentioning

confidence: 99%

A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

Kim

Roy

2006

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

The parasitic bipolar leakage and the large subthreshold leakage due to high floating-body voltage reduce the noise margin and increase the delay of the circuits in the partially depleted silicon-on-insulator (PD/SOI). Differential cascode voltage switch logic (DCVSL) has circuit topologies susceptible to the leakage currents. In this paper, we propose a new circuit style to effectively handle the leakage problems in PD/SOI DCVSL. The proposed low-swing DCVSL (LS-DCVSL) uses the small internal swing to prevent the body of evaluation transistors from being charged to high voltage and, hence, suppress the leakages in DCVSL. Simulation results show that the proposed LS-DCVSL five-input XOR circuit is 33% faster than DCVSL five-input XOR circuit. In addition, the proposed circuit does not experience noise margin reduction due to pass-gate leakage.

show abstract