Fast and energy-efficient Manchester carry-bypass adders

Perri, Stefania; Corsonello, Pasquale; Pezzimenti, F.; Kantabutra, Vitit

doi:10.1049/ip-cds:20040807

Cited by 20 publications

(6 citation statements)

References 4 publications

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“…With an analogous reasoning, taking into account Equation (10), the switching probabilities given in Equation (11) are computed for the signals GGP [i] and GGG [i] .…”

Section: Advantages Over the Previous Parallel-prefix Algorithmmentioning

confidence: 99%

“…The XOR/XNOR outputs are then inputted to two Dynamic Domino gates that compute the signal GP [i] and GG [i] according to Equations (2) and (4). The four-inputs DOT operators, employed in the parallel-recursive and post-processing stages, consist of a four-bits Dynamic Domino AND gate and a four-bits Manchester-Carry chain [11]. The signals GGG and GGP are half-latched in order to realize an efficient pipeline: the clock signal clk feeds the dynamic gates of the pre-processing stage and it regulates the running of the parallel-recursive stage, which produces the signals GGG and GGP; the latter are evaluated by the post-processing stage when clk is low.…”

Section: Transistor-level Implementationmentioning

confidence: 99%

See 1 more Smart Citation

Energy‐efficient single‐clock‐cycle binary comparator

Frustaci

Perri

Lanuzza

et al. 2012

Circuit Theory & Apps

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“…With an analogous reasoning, taking into account Equation (10), the switching probabilities given in Equation (11) are computed for the signals GGP [i] and GGG [i] .…”

Section: Advantages Over the Previous Parallel-prefix Algorithmmentioning

confidence: 99%

Section: Transistor-level Implementationmentioning

confidence: 99%

Energy‐efficient single‐clock‐cycle binary comparator

Frustaci

Perri

Lanuzza

et al. 2012

Circuit Theory & Apps

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show abstract

“…Simulatio adder give a worst case propagation del enhanced 32-bit CLA adder implemented (Multiple output enable disable CMOS di designed in [8]. In [9] a new modified M Carry-propagation delay in the chain is r oriented architecture. Carry-skip routes propagate quickly, avoiding long carry p Computational delay for 32-bit adder is 2.2n…”

Section: … …mentioning

confidence: 99%

High speed Manchester Carry chain with carry-skip capability

Asha

Senthilkumar

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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Design of adder is the most focused area in VLSI systems. In this paper, multi-output domino Manchester carry chain with carry-skip capability is proposed. In the proposed design, even and odd carries are computed independently by two parallel carry chains. Carry-skip capability is applied to the odd carry chain which reduces the worst case critical path delay. The circuits are designed and simulated using Cadence Virtuoso tool with CMOS 180nm TSMC technology and IBM 130nm technology in LT SPICE IV. The proposed 64-bit Double chain Manchester Carry chain with carry-skip Adder shows a delay reduction of 52% compared to the Double chain Manchester Carry chain. The proposed Double chain Manchester carry chain with Carry-skip logic allows the elimination of intermediate buffers, thus retaining its area. Keywords-Carry Look-ahead Adder (CLA), Manchester Carry Chain (MCC), multi-output Domino, Carry-skip logic.

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“…12,13 Amidst the several types of parallel adders, CLA is highly popular. 14,15 At first, Weinberger and Smith introduced the CLA method in Ref. 16.…”

Section: Introductionmentioning

confidence: 99%

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Hasan

Chowdhury

Faruqe

et al. 2023

Engineering Reports

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This research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures.

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Fast and energy-efficient Manchester carry-bypass adders

Cited by 20 publications

References 4 publications

Energy‐efficient single‐clock‐cycle binary comparator

Energy‐efficient single‐clock‐cycle binary comparator

High speed Manchester Carry chain with carry-skip capability

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

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