Silicon On Insulator SOI technology allows for high performance by eliminating latch up in bulk CMOS, improving the short-channel e ect, and soft error immunity. However, the oating body e ect in SOI devices and the resulting hysteresis poses major challenges for dynamic circuit designers. In this paper, we describe implementation of a 64 bit adder and some of the techniques used to overcome the parasitic bipolar discharge e ect while maintaining performance.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.