A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

Asyaei, Mohammad

doi:10.1016/j.vlsi.2015.06.003

Cited by 50 publications

(19 citation statements)

References 37 publications

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“…UNG is a commonly used parameter to evaluate the noise robustness of the dynamic circuit. 18–22 The UNG is described as the value of noise amplitude at the input which produces the same noise amplitude at output. 15 UNG = ( Vnoise : Vnoise = Vout ) .…”

Section: Resultsmentioning

confidence: 99%

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Noise measurement in high-speed domino pseudo-CMOS keeper

Poongodi

2018

Measurement and Control

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Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.

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Section: Resultsmentioning

confidence: 99%

“…Figure 6 shows OR gate with two inputs using a voltage comparison based domino (VCD). 18 In this logic, the output voltage is produced by using a sense amplifier. The sense amplifier compares the voltage across the pull-down network to produce the output.…”

Section: Limitations Of Existing Keeper–based Domino Circuitsmentioning

confidence: 99%

Noise measurement in high-speed domino pseudo-CMOS keeper

Poongodi

2018

Measurement and Control

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“…Multiple thresholds can be achieved by multiple channel doping, multiple oxide CMOS fabrication, multiple channel length, and multiple body bias. Asyaei has presented a new leakage‐tolerant domino circuit for lower power consumption and higher noise immunity without significant delay increase in wide fan‐in gates. A sense amplifier is used to find out the difference between the voltages across the pull‐down network (PDN) in order to correct the output.…”

Section: Literature Reviewmentioning

confidence: 99%

ONOFIC‐based leakage reduction technique for FinFET domino circuits

Magraiya

Gupta

2018

Circuit Theory & Apps

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Summary A new technique ON/OFf logIC (ONOFIC) is proposed in this paper for designing domino logic circuits in fin‐field effect transistor (FinFET) deep submicron technology. In this technique, a block named ONOFIC is inserted between pull‐up network (PUN) and pull‐down network (PDN) of domino circuits. The proposed technique is simulated in FinFET short gate (SG) and low power (LP) mode. The subthreshold current which plays a major role to determinate leakage power is very low in this technique. Two‐, 4‐, 8‐, and 16‐input OR gates are simulated with 32‐nm node FinFET technology. In FinFET LP mode, the subthreshold leakage power of the proposed technique is reduced by 15% to 24.3% at 25°C and reduced by 8.71% to 23.4% at 110°C compared with standard domino circuits. The subthreshold leakage power of the proposed circuit is reduced by 19.2% to 57.3% at 25°C and reduced by 17.6% to 60.7% at 110°C compared with leakage control transistor (LECTOR)‐based circuits. In FinFET SG mode, the subthreshold leakage power of the proposed technique is reduced by 7.69% to 17.7% at 25°C and reduced by 0 to 7.85% at 110°C compared with standard domino circuits. The subthreshold leakage power of the proposed circuit is reduced by 60.4% to 73.9% at 25°C and reduced by 45.1% to 65.5% at 110°C compared with LECTOR‐based circuits. The proposed technique is also efficient to reduce subthreshold leakage power in deep nanometer technology nodes from 7 to 20 nm.

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“…The only drawback of this circuit is that large number of transistor is used so areas overhead take place [7]. Another type of domino circuit design is Diode footed which is the most prominence technique for mitigation of power consumption and enhances the UNG of the circuit [11][12][13].…”

Section: (A) Footless Standard Domino Logic and Footed Standard Domino mentioning

confidence: 99%

Comparative Analysis of Various Domino Logic Circuits for Improvement of Power and Delay Calculation

Shrivastava¹,

Rawat²

2017

IJCA

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The urge of high performance and dynamic functionalities in an integrated circuit has led to aggressive technology scaling over the years. The supply voltage (V DD ), device threshold voltage (V th ) and the device geometry are expected to be scaled further with this trend. Which results in reducing the short channel effects and increased transistor OFF-state current (I OFF ). Additionally leakage currents, higher operating frequency and on die transistor count will lead to increase in total power dissipation. Dynamic logic technique is preferred over static logic technique for the higher performance circuit due to lesser delay which enhances the speed of the circuit and overall capacitance is low compare to CMOS which reduces the power consumption. In this paper we have calculate the Average power consumption and delay of various domino circuits provided with 8 input OR gate, comparison of power, delay, and Unit Noise Gain (UNG) of different topologies. The simulation is performed in HSPICE at 65nm and 45nm process technology with supply voltage 1V and 0.9V and operating temperature of 27⁰ C at 100 MHz for fair comparison of results. We have also calculated the power consumption and delay with the variation of keeper ratio in all the existing technique at 65nm and 45nm process technology.

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A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology

Cited by 50 publications

References 37 publications

Noise measurement in high-speed domino pseudo-CMOS keeper

Noise measurement in high-speed domino pseudo-CMOS keeper

ONOFIC‐based leakage reduction technique for FinFET domino circuits

Comparative Analysis of Various Domino Logic Circuits for Improvement of Power and Delay Calculation

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