ONOFIC‐based leakage reduction technique for FinFET domino circuits

Magraiya, Vijay Kumar; Gupta, Tarun Kumar

doi:10.1002/cta.2583

Cited by 9 publications

(3 citation statements)

References 22 publications

(32 reference statements)

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“…However, through literature survey and review analysis many of the evaluation technique still left for the further investigation. Among them we found the ONOFIC approach, which uses the single threshold voltage throughout the device circuit [24,25]. So, in this section, our proposed device circuit simulation is compared with the ONOFIC technique as inverter, NOR and NAND in terms of power dissipation and propagation delay.…”

Section: Resultsmentioning

confidence: 99%

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

Singh

Raj

2020

Silicon

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In this paper, a new technique ONOFIC is proposed and implemented for designing the SiGe heterojunction 2D double gate Vertical t-shaped TFET as an inverter circuit for low power applications. Initially, simulation done for both P-type and N-type of Vertical tTFET with same attributes using Sentaurus TCAD simulation tool. Thereafter, mixed mode technique is employed to understand the inverter circuit simulation's electrical characteristics and circuit efficiency. The workfucntion used for n-type Vertical TFET is 4.5 eV and for p-type Vertical TFET is 5.6 eV respectively. A 2D analytical model also implemented to capture the affecting parameters of leakage current and depletion length of the proposed model. Moreover, a new block technique named ONOFIC is inserted between the pull-up network and pull-down network of the circuit to regulator the trade-off between the power dissipation and reduced device dimensions. The method offers an excellent agreement between the propagation delay and power dissipation for designing efficient logic circuit. This article compares the efficiency of logic circuit like NAND, NOR and inverter circuit by estimating the power-delay product (PDP) with the conventional logic designs. The performance result show that the proposed model significantly reduces the leakage current for low power circuit applications.

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Section: Resultsmentioning

confidence: 99%

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

Singh

Raj

2020

Silicon

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“…Moradi et al [11] designed high performance domino circuits including leakage and proposed several logic circuits using FinFET device which is useful for reducing total leakage power. Magraiya et al [12,13] also worked for reduction of subthreshold leakage power in FinFET domino circuits with the help of ONOFIC & ONOFIC pull-up approach and achieved subthreshold leakage reduction.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current

Magraiya

Gupta

Garg³

2022

Silicon

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The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36-95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24-99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively. HighlightsThe major contributions of the paper are as follows:1. A comprehensive analysis on the state-of-the-art leakage reduction techniques.2. An analysis of the leakage reduction using CNTFET devices.3. An improved leakage reduction technique using dual chiral CNTFET in standard footerless and LECTOR based domino circuits.4. The simulation results show subthreshold leakage current reduction upto 97.3% at 25°C and 99.76% at 110°C.

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“…Moradi et al [11] designed high performance domino circuits including leakage and proposed several logic circuits using FinFET device which is useful for reducing total leakage power. Magraiya et al [12,13] It is observed from the above research work that the existing leakage reduction techniques with CMOS & FinFET devices are still not minimizing the leakage current e ciently. Further there is very less analysis on the leakage current of circuits with CNTFETs.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

Magraiya¹,

Gupta²,

Garg³

2021

Preprint

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The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36- 95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24- 99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively.

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ONOFIC‐based leakage reduction technique for FinFET domino circuits

Cited by 9 publications

References 22 publications

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current

Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

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