A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes, Benjamín T.; Paulina, German; Sánchez, Rubén Argüero; Mandolesi, Pablo S.; Hueda, Mario R.

doi:10.1007/s10470-015-0578-z

Cited by 9 publications

(11 citation statements)

References 32 publications

(54 reference statements)

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“…Table 2 compares the performances of the proposed TI ADC with the similar studies from the literature. Although [6] and [21] are also TI type of ADC examples, they use different core ADC architectures. Therefore, comparison of this work with them may not be fair.…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…In terms of layout area, it is not fair to make comparison since having lower resolution. However, it may be considered that the area of this design is much lower than that of [6].…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…The other works included fast flash or different ADC core architectures and fast timing control circuits for TI ADC designs. 6. Schematic of the comparator circuit technology.…”

Section: Preliminary Workmentioning

confidence: 99%

“…Here, frequency and phase of the sampling control pulses for n number of flash ADCs are very critical. The sampling frequency of each flash ADC is calculated as F s = N/T , where N is the number of interleaving, T is the period of sampling for each Flash core [6]. Hence, it becomes possible to achieve very high sampling rates for time-interleaved ADCs [7,8].…”

Section: Introductionmentioning

confidence: 99%

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A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Aytar

Tangel

Afacan

2017

Journal of Electrical Engineering

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This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

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Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…In terms of layout area, it is not fair to make comparison since having lower resolution. However, it may be considered that the area of this design is much lower than that of [6].…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…The other works included fast flash or different ADC core architectures and fast timing control circuits for TI ADC designs. 6. Schematic of the comparator circuit technology.…”

Section: Preliminary Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Aytar

Tangel

Afacan

2017

Journal of Electrical Engineering

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“…However, the fabrication errors result in a variety of mismatch errors, constricting the conversion precision of the TIADC. Among them, the main mismatches are offset, gain, and timing mismatches [1,2].…”

Section: Introductionmentioning

confidence: 99%

A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs

et al. 2016

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A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics calibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel samples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work, the offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the timing mismatch is estimated by performing the correlation calculation of the outputs of subchannels and corrected by an improved fractional delay filter based on Farrow structure. Applied to a four-channel 12-bit 400 MHz TIADC, simulation results show that, with calibration, the SNDR raises from 22.5 dB to 71.8 dB and ENOB rises from 3.4 bits to 11.6 bits for a 164.6 MHz sinusoidal input. Compared with traditional methods, the proposed schemes are more feasible to implement and consume less hardware resources.

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A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

Solis

Bocco

Galetto

et al. 2021

Circuit Theory & Apps

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This paper presents the design, implementation, and measurements of a 4 GS/s, 8-bit resolution, time-interleaved (TI) analog-to-digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI-ADC in the process used. An energy-efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on-chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low-voltage differential signaling interface is included to transmit the samples off-chip without any decimation. The TI-ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv-step and owing to the efficient interleaved architecture the full TI-ADC achieves a peak FOM of 171fJ/conv-step (526fJ/conv-step at Nyquist).

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A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Cited by 9 publications

References 32 publications

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

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