Digital-to-analog converters (DACs) with bandwidths larger than 70 GHz and sampling rates in excess of 170 GS/s will soon be required in ultra-high speed communication applications such as coherent optical transceivers operating at symbol rates of 140 GBd and beyond. Frequency interleaving has been proposed as a way to break the bandwidth bottleneck in such applications. Splitting the input signal into multiple frequency bands reduces the required bandwidth per interleaved DAC and therefore it enables the synthesis of greater bandwidth signals in the reconstructed output. Elaborate digital signal processing (DSP) is required to seamlessly stitch together the sub-bands and compensate the errors of the analog signal path, which would otherwise severely degrade the performance of the communication system. Adaptive DSP techniques are required to automatically compensate errors caused by process, voltage, and temperature variations in the technology (e.g., CMOS, SiGe, etc.) implementations of the data converters, and therefore ensure high manufacturing yield. These techniques must operate in background mode to avoid interfering with the normal operation of the communication system. This work introduces an adaptive background compensation scheme for frequency interleaved DACs (FI-DACs). The primary application example is a 128 GBd QAM16 coherent optical transceiver. However, the technique is applicable to other types of communication transceivers, and it can be generalized to arbitrary signals, as long as they are stationary or quasi-stationary and have a wideband continuous spectrum. The key elements of the proposed technique are a MIMO equalizer and the backpropagation algorithm. Numerical simulation results for the aforementioned application example show that the signal to noise and distortion ratio (SNDR) of the FI-DAC is boosted by more than 25 dB when the proposed compensation technique is applied in the presence of typical analog mismatches. Furthermore, the optical signal to noise ratio penalty of the optical transceiver is reduced from 6 dB to 0.1 dB. INDEX TERMS Background calibration, error backpropagation, frequency interleaving DAC, high-speed optical transmitter
This paper presents the design, implementation, and measurements of a 4 GS/s, 8-bit resolution, time-interleaved (TI) analog-to-digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI-ADC in the process used. An energy-efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on-chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low-voltage differential signaling interface is included to transmit the samples off-chip without any decimation. The TI-ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv-step and owing to the efficient interleaved architecture the full TI-ADC achieves a peak FOM of 171fJ/conv-step (526fJ/conv-step at Nyquist).
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