A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

Abstract

This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-µW ultra-lowpower operation. The proposed switching feedback can seamlessly change the DPLL from sampling operation to sub-sampling operation without disturbing the phase-locked state of the DPLL to reduce the number of building blocks that works at the oscillator frequency, leading to significant power reduction. With the reduced number of high-frequency circuits, scaling the reference frequency is fully used to reduce the power consumption of the DPLL. Together with an out-of-dead-zone detector and a duty-cycled frequency-locked loop running in the background, the switching feedback achieves robust frequency and phase acquisition at start-up and helps the sub-sampling PLL recover when large phase and frequency disturbances occur. A transformer-based stacked-g m oscillator is proposed to minimize the power consumption while providing the sufficient swing to drive the subsequent stages. A truncated constant-slope digital-to-time converter is proposed to improve the power efficiency while retaining good linearity. The proposed fractional-N DPLL consumes only 265 µW while achieving an integrated jitter of 2.8 ps and a worst case fractional spur of −52 dBc, which corresponds to a figure of merit (FOM) of −237 dB.

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

“…At the CKVGs' rising edges, the corresponding SWDs fall (5.1 and 5.2). Once both the SWDs become LOW, they are reset (6) to HIGH simultaneously (7). Consequently, the PFD outputs an activelow pulse-pair on the SWDs.…”

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

“…PLLs. Many different DTC implementations have been devised, such as constant-slope (CS) [34]- [38], variableslope (VS) [39]- [42], and path-selection (PS) based topologies [10], [19], [43], [44]. Considering the feasibility of standard cell implementation, VS and PS DTCs are preferred.…”

A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

“…The power consumption and the phase noise of a digital controlled oscillator (DCO) determine the digtal phase locked loops (DPLL) performance. The trend towards low power design of DPLL [1][2][3][4][5] is driven by the requirements of the low power and low cost communication systems, therefore the low power design of DCOs appeared.…”

“…Nevertheless, this structure suffers drawbacks of low frequency range and extra area of inductors. Another toplogy with transformers [2] can also improve the voltage effeciency. But this circuit suffers the difficulty of transformers.…”