A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Abstract

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs-the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges-and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below −59 dBc. Under considerable supply or temperature variations, the worst spur still remains below −51.7 dBc without any background calibration tracking. Index Terms-Digital-to-time converter (DTC), fractional spur, phase-locked loop (PLL), process voltage and temperature (PVT), time-mode arithmetic unit (TAU). I. INTRODUCTIONT HE sub-sampling technique [1], [2], [3], [4], [5] and, more specifically, the narrow-range phase-detection concept [6], [7] have contributed to a significant improvement of phase noise (PN) in phase-locked loops (PLLs). Such techniques ensure that the phase detector (PD) can expect a

Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop

“…The SC strategy proposed in Section IV is applied in an off-line manner to a fractional-N digital PLL chip modified from [21], which exhibits fractional spurs due to the FREF-induced DCO interference. The PLL operational information, i.e., sequences representing ⃗ φ R and ⃗ φ PD , is stored in an on-chip memory for debugging.…”

“…The content of the LUT is calibrated by a least mean squre (LMS)-based algorithm [21] sketched in Fig. 9 (bottom-left): After the φ crs code is used, the resulting TDC output D TDC is scaled by the step-control factor µ crs and then demultiplexed to the accumulator associated with the φ crs code.…”

“…A simple sinusoidal waveform also makes it possible to agilely adjust the amplitude and phase of the SC pattern according to the precisely known PLL's transfer function when the PLL hops to nearby channels, thereby saving the efforts on recalibration. Second, by exploiting the condition that the self-interference signals are synchronized with the PLL's output-clock phase, injecting the canceling signal can be achieved by simply reusing the same hardware as in some of the aforementioned strategies mitigating the PD-nonlinearityraised spurs, e.g., a lookup table (LUT) predistorting the PD's nonlinearity according to the expected PLL output phase [6], [7], [21].…”

“…Section III analyzes the features of self-interference, especially that injected into the DCO, paving the way for developing the SC strategy in Section IV. Section V discloses how the proposed SC strategy was applied to a fabricated digital PLL chip modified from [21]. Then, Section VI demonstrates the measured cancellation performance.…”