A Fully Synthesizable Fractional-<i>N</i> MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Liu, Bangan; Zhang, Yuncheng; Qiu, Junjun; Ngo, Huy Cu; Deng, Wei; Nakata, Kengo; Yoshioka, Toru; Emmei, Jun; Pang, Jian; Narayanan, Aravind Tharayil; Zhang, Haosheng; Someya, T.; Shirane, Atsushi; Okada, Kei

doi:10.1109/tcsi.2020.3035373

Cited by 32 publications

(19 citation statements)

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“…A reason for the less fine frequency resolution is due to the nonminimum size of the selected cells to cover the required tuning range of the fine bank. Although it is less flexible to tweak variable capacitance with limited choices of standard cells, the frequency resolution can still be improved by selecting smaller size gates and adding one more medium bank as done in [20]. Also, the noise coupled from power supply is susceptible to the reference spur as well because no low dropout regulators are employed for this work.…”

Section: Resultsmentioning

confidence: 99%

“…In [15], multistage soft injection was proposed, but the frequency resolution is limited. A more effective way can be using a digital-to-time converter (DTC) to align the phase of the injecting reference clock [16]- [20]. Although a DTC basically features finer resolution than a TDC, the automatic P&R introduces unpredictable parasitic elements that worsen the jitter and linearity compared with a custom-designed one.…”

Section: Introductionmentioning

confidence: 99%

“…To tackle this issue, recently, the essential idea is to reduce the range of the variable-slope DTC in a fractional-N PLL. In [16], [18], and [20], a segmented coarse-to-fine DTC was proposed, where the 8-bit variable-slope fine DTC is relatively linear. Its smaller area results in less parasitic elements as well.…”

Section: Introductionmentioning

confidence: 99%

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A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

2022

IEEE J. Solid-State Circuits

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A standard-cell-based fractional-N synthesizable phase-locked loop (PLL) [or multiplying-delay-locked loop (MDLL)] is proposed, where the multiple phases of the threestage ring digitally controlled oscillator (DCO) are utilized for injection. The required digital-to-time converter (DTC) range is reduced to one third of the DCO's period, resulting in higher linearity, less jitter, lower power consumption, and smaller area. The issue of the mismatches among DCO's stages is solved by the proposed dithering-assisted local skew calibration, which removes the skews in the injection path and smears out the periodic pattern at the PLL side to reduce spurs. Most of the dithering noise is suppressed by the injection locking and the phase tracking loop. Measured at 1.0095-GHz output frequency with 24-MHz reference frequency, with the proposed solution, the integrated root-mean-square (rms) jitter can be reduced from 6.40 to 2.55 ps, and the power consumption is 3.36 mW. This translates to −226.6-dB figure of merit (FoM) and −232.8-dB FoM ref . The measured fundamental fractional spurs range from −56 to −45 dBc.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

2022

IEEE J. Solid-State Circuits

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“…12. Unlike the existing LuT construction methods in [35] and [36], which usually needs more than hundreds of reference cycles to construct the LuT, the LuT construction proposed in this work is based on the combination of successive approximation (SAR) logic and the LPF process. The SAR logic is implemented based on the binary search method, and the LPF process is based on the digital accumulator.…”

Section: B Adaptive Lookup Table Constructionmentioning

confidence: 99%

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Qiu

Sun

Liu

et al. 2021

IEEE J. Solid-State Circuits

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In this article, a mixed-signal, 32-kHz referencebased 2.4-GHz fractional-N over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional 1× sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digitalto-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs' construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm 2 , and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional-N modes with the loop-bandwidth (BW loop ) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively.

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“…A dual-loop configuration was used to achieve a low-frequency error. For the fractional-N clock generators, the multiplying delay-locked loops (MDLLs) were reported in [19]- [20]. The digital calibration schemes were adopted to achieve excellent jitter and spur performance.…”

Section: Introductionmentioning

confidence: 99%

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

Liu

2021

IEEE Access

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An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper. The bootstrapped ring oscillator can boost the output voltage to a higher level than the supply voltage. Thus, the oscillator can be operated in low-supply-voltage applications. MOS varactor is used in the bootstrapped capacitor to reduce the area cost. Circuit analysis and simulated verification were performed for an optimized design. The interpolated DCO has multiphase outputs and a high operating frequency. The test chip was implemented in a 90-nm CMOS process, and the core area was 60 × 117 μm 2. The power consumptions at 1160 MHz and 20 MHz were 912.6 μW (at 0.6 V) and 2.94 μW (at 0.2 V), respectively. In the worst-case jitter performance, the root mean square (RMS) jitters were less than 0.42%. INDEX TERMS Bootstrapped, digitally controlled oscillator (DCO), interpolation, multiphase, phaselocked loop (PLL).

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A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Cited by 32 publications

References 50 publications

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator

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