A 24&amp;#x03BC;W 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching

Wu, Meng-Hsuan; Li, Hung-Sung

doi:10.1109/cicc.2013.6658424

Cited by 6 publications

(5 citation statements)

References 4 publications

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“…11 In Huang et al, 12 an external voltage source was used to set the window size for biomedical signal conversion. In contrast with our proposed switching scheme, the 2-step decision switching scheme reported in Chung et al 13 has a smaller window and hence results in smaller SFDR and SNDR performance improvement. In Chung et al, 13 a 2-step decision DAC switching scheme was employed to effectively improve ADC linearity.…”

Section: Introductionmentioning

confidence: 77%

“…[11][12][13] However, auxiliary circuits using 2 additional comparators exhibit offset deviation among the 3 comparators. [11][12][13] However, auxiliary circuits using 2 additional comparators exhibit offset deviation among the 3 comparators.…”

Section: Introductionmentioning

confidence: 99%

“…[11][12][13] However, auxiliary circuits using 2 additional comparators exhibit offset deviation among the 3 comparators. In Chung et al, 13 a 2-step decision DAC switching scheme was employed to effectively improve ADC linearity. The linearity improvement was negligible when the window size was not large enough.…”

Section: Introductionmentioning

confidence: 99%

“…Window-switching techniques have been proposed for DACs to avoid unnecessary capacitor switching. [11][12][13] However, auxiliary circuits using 2 additional comparators exhibit offset deviation among the 3 comparators. 11 In Huang et al, 12 an external voltage source was used to set the window size for biomedical signal conversion.…”

Section: Introductionmentioning

confidence: 99%

“…The linearity improvement was negligible when the window size was not large enough. In Chung et al, 13 a 2-step decision DAC switching scheme was employed to effectively improve ADC linearity. In contrast with our proposed switching scheme, the 2-step decision switching scheme reported in Chung et al 13 has a smaller window and hence results in smaller SFDR and SNDR performance improvement.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

Yen

Tsai

2017

Circuit Theory & Apps

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This paper presents an energy-efficient 12-bit successive approximation-register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary-window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spuriousfree dynamic range and signal-to-noise-and-distortion ratio. The ADC prototype occupies an active area of 0.12 mm 2 in the 0.18-μm CMOS process and consumes a total power of 0.6 mW from a 1.5-V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7-dB signal-tonoise-and-distortion ratio and 83-dB spurious-free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure-of-merit of 43 fJ/conversion-step. KEYWORDSA/D converter (ADC), binary window, D/A converter (DAC), successive approximation register (SAR)

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Section: Introductionmentioning

confidence: 77%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

Yen

Tsai

2017

Circuit Theory & Apps

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Asynchronous SAR ADC with self‐timed track‐and‐hold

Bae,

Lee,

Seong

et al. 2023

Electronics Letters

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This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases.

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An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components

San

Sugawara

Hotta

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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A 12-bit algorithmic (cyclic) ADC is designed and fabricated in 90nm CMOS, and only occupies as small active area as 0.037mm 2 . With the proposed radix-value self-estimation scheme for a non-binary 1-bit/step architecture, the accuracy requirement on analog components is largely relaxed. Therefore, the implementation of analog circuits such as amplifier and comparator becomes simple, and high-density MOM capacitors can be used to achieve small area. Furthermore, the novel radixvalue self-estimation technique can be realized by only simple logic circuits without any extra analog input, so that the total active area of ADC is dramatically reduced. The prototype ADC achieves 62.3dB SNDR at 1.4V power supply and 1.25Msps (20MHz clocking) using a poor DC gain amplifier as low as 45dB and MOM capacitors without any careful layout techniques to improve the capacitor matching. The measured DNL is +0.94/-0.71LSB and INL is +1.9/-1.2LSB at 30kHz input.

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A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching

Cited by 6 publications

References 4 publications

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

Asynchronous SAR ADC with self‐timed track‐and‐hold

An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components

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