A 20 ps/G Si Bipolar IC Using Advanced SST with Collector Ion Implantation

Konaka, Shinsuke; Amemiya, Yoshihito; Sakuma, K.; Sakai, T.

doi:10.7567/ssdm.1987.s-i-1

Cited by 39 publications

(2 citation statements)

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“…However, the technique we have used will allow specific devices, NPN or PNP, to be optimised, if required. In many ways this "sacrificial oxidation" technique is analogous to that of the "selective implanted collector" (SIC) but, we believe, has the advantage of superior control, manufacturability and flexibility [3], [4]. Figure 10 shows an SEM micrograph of an NPN transistor during processing.…”

Section: Device Results: Enhancedmentioning

confidence: 99%

New high-performance complementary bipolar technology featuring 45-GHz NPN and 20-GHz PNP devices

et al. 1999

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A new high performance silicon complementary bipolar technology is introduced. In addition a novel process "enhancement" technique based on a local oxidation is described and demonstrated and NPN devices with cut-off frequencies up to 45GHz and PNP devices of 20GHz have been fabricated. We propose that the technique we have used will allow specific transistors within a circuit to be optimised, as required.

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Section: Device Results: Enhancedmentioning

confidence: 99%

New high-performance complementary bipolar technology featuring 45-GHz NPN and 20-GHz PNP devices

et al. 1999

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“…Recent progress in advanced self-aligned bipolar technology has resulted in high-perfonnance ECL circuits with sub-75ps gate delays (1)(2)(3)(4)(5). To achieve such high performance, advanced bipolar devices generally have thin bases, shallow emitters, and, in particular, reduced parasitics.…”

Section: Introductionmentioning

confidence: 99%

Comparison of Effects of Ionizing Radiation and High-Current Stress on Characteristics of Self-Aligned Bipolar Transistors

Chen¹,

Norum²,

Ning³

1988

Extended Abstracts of the 1988 International Conference on Solid State Devices and Materials

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4 Gbit/s optical receiver IC's using high‐speed bipolar process “ESPER”

Deguchi

Tahara

Takada

et al. 1990

Electron Comm Jpn Pt II

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A high‐speed silicon bipolar process (ESPER) is developed using the two‐level poly Si process. The ESPER transistor reduces the collector‐base capacitance by extending the poly Si base electrode onto a thick oxide film. In addition, the base resistance is reduced by forming the poly Si extended base electrode and emitter with the self‐aligned structure. An optical receiver IC was fabricated using the combination of the ESPER transistor and the trench isolation structure. The preamplifier and the decision circuit of the optical receiver IC have been evaluated. The preamplifier frequency bandwidth of 3.6 GHz was confirmed and the decision sensitivity of 90 mV at 4 Gbit/s.

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A 20 ps/G Si Bipolar IC Using Advanced SST with Collector Ion Implantation

Cited by 39 publications

References 0 publications

New high-performance complementary bipolar technology featuring 45-GHz NPN and 20-GHz PNP devices

New high-performance complementary bipolar technology featuring 45-GHz NPN and 20-GHz PNP devices

Comparison of Effects of Ionizing Radiation and High-Current Stress on Characteristics of Self-Aligned Bipolar Transistors

4 Gbit/s optical receiver IC's using high‐speed bipolar process “ESPER”

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