4 Gbit/s optical receiver IC's using high‐speed bipolar process “ESPER”

Abstract

A high‐speed silicon bipolar process (ESPER) is developed using the two‐level poly Si process. The ESPER transistor reduces the collector‐base capacitance by extending the poly Si base electrode onto a thick oxide film. In addition, the base resistance is reduced by forming the poly Si extended base electrode and emitter with the self‐aligned structure. An optical receiver IC was fabricated using the combination of the ESPER transistor and the trench isolation structure. The preamplifier and the decision circuit of the optical receiver IC have been evaluated. The preamplifier frequency bandwidth of 3.6 GHz was confirmed and the decision sensitivity of 90 mV at 4 Gbit/s.