373ChemInform Abstract at amospheric pressure has been studied in order to minimize autodoping from the highly doped Si substrate. Using a conventional vertical reactor and disilane, the temp. can be reduced to 800 rc C. The epilayer exhibits good crystalline quality (defect density < 1/cm2) and the thickness of the transition layer from highly doped Si to the epilayer is reduced to below 0.3 µm. The bipolar transistor fabricated in the epilayer of less than 1 µm thickness shows good electrical characteristics (breakdown voltage > 25 V).
This ECL device achieves lOOk-gate integratiun with a standard cell layout approach, A standard·cell CAD architecture enables high-power ECL gate cells and freely placed megacells to be in· tegrated on a chip with fixed-pattern power supply buses. The 3"m.thick top (4th) metal layer is dedicated to the main power bnses.Under the main power buses are densely packed poly cells (polycell seas) and megacells surrounded by global chip routing channels and fixed-pitch sub· power buses, in the 3rd metal layer and orthogonal to the main power buses ( Figure 1). This structure gives the chip a density twice that of conven· tional ECL gate arrays and a more flexible layout without com promising high. power capacity.The die of the 60W chip is 14.72mm square, with lOOk equivalent gates and a maximum gate density of 1255 gates/mm'. This chip is mounted on the 56 I-pin PGA package with TAB leads and bumps on the die with 100"m pitch. (Figure 2) The thermal resistance Uunction.ambient) of the package is less than 10 C/W at an air flow of 10m/so Maximum dissipation in this package is 60W.A wafer process involves an emitter· base self-aligned struc· ture with polysilicon electrodes and resistors (ESPER), rom· bined with U·FOX isolation and four metal layers with a mini mum 2,6"m routing pitch'. Metal wires on 2nd metal layer and orthogonal 1st metal wires lying under 3rd metal sub-power buses form the global channels with a 2.6"m pitch uutside the polycell seas and megacells. In the polycell sea, the 2,6"m pitch 2nd metal wire; and the 5.2"m.pitch 3rd metal wires form inter· cell port routing over intra· cell transistor and resistor patterns on 1st metal layer.CAD lays out the chip with 2·level hierarchical steps.Step 1 is the chip floor plan using megacells and macro blocks consisting of logically connected polycells. The polyeell sea is assigned for the macro block and surrounded by the exclusive global channels. Megacells can be placed anywhere by CAD, the 3rd metal sub· power buses being substituted with ;lrd metal power supply pat· terns in their budy (Figure 3). External macroblock ports are planned for positioning at the periphery of the poly cell sea so that external connections of macroblocks use only the global channels. That is, routing inside macroblocks in step 2 is not affected by external connection wiring, which is nsually very long, and CAD produces a high.quality layout easily.This blocked poly cell sea reduces poly cell size more com· plr.tely than a conventional standard·cell or channel-less approach in which, with densely packed cells but no exclusive global chan· nels, each cell should have feed-through channels fur global can· nection only to pass through the cell. This approach does not have this layuut loss, and can have a density about twice that of the conventional approach with the same process technology. This is a 500/0 cut in cell size and an average 300/0 cut in wiring length (Figure 4). 94In the power bus scheme of Figure 1, the horizontal fixed main power buses (4th metal layer) and the vertical ...
In recent ULSI technology, reduction of parasitic capacitances has been playing an important role in obtaining high speed performance of the devices.SST[lI and SICOS[21 were developed to satisfy this purpose. In these processes, polysilicon base contacts were formed on field oxide and connected with active base region. Therefore, these processes were not so easy. Thus, we have developed SPEG technique which makes it possible to form active region on Si-substrate and contact region on Si02 spontaneous1 using infrared heated barrel reactors. Because, much of the silicon epitaxial growt K done in the,semiconductor industry i s done in,infrared,heated barrel reactors. By using SPEG technique, we have, developed, the slmpler bipolar process which realize the transistor structure reducing arasitic capacitances. We fabricated ECL ring oscillators and evaluated the electrical c c : aracteristics.We have successfully achieved SPEG technique using commercial barrel reactor and Si2H6 for the first time. SPEG was done under the growth condition of 9OO*C, 80 Torr, Si2H6 1%/H2 4 slm, and HZ 120 slm. The growth rate was 70nm/min. The thickness uniformity of within wafer was + / - 2%.The olysilicon layer of SPEG smoothly connected with the epitaxial layer of SPEG even in t F: in films such as 300 nm. Figure 1 shows the fabrication process of the bipolar transistor using SPEG technique, This process is a simpler and shorter process, therefore it realizes a lower cost and a higher yield. Figure 2 shows the cross-sectional SEM picture of the sample, Very smooth structure of SPEG was erformed on LOCUS-SiO2. Figure 3, 4 and 5 show the electrical characteristics of t R e bipolar Tr. with base contacts on SiO2. From Fig. 3 , it is apparent that C-E and E-B junctions were well fabricated. From Fig. 4, B VCEO was about 7 V a n d no leakage current was observed. From these results, we verified the epitaxial layer o f SPEG was good crystalline qualit and the polysilicon layer of SPEG was well used as base contacts. The experimenta Y 41-stage (low power type) and 25-stage (high power type) ECL ring-oscillators (F.I. =1, F . O . = l ) were used to evaluate swltching characteristics. The propagation delay time (t dl versus power (Pd) characteristics are plotted in Fig. 6. The power-delay product of t 1 e low power type was 0.12 pJ and that of the high power type was 0.4 pJ. The cut-off frequency (ft) was 16 GHz at VCE = 3V. The C-B junction capacitance (CCB) of the low power type was 3 fF and that o f the high power type was 10 fF. Our bipolar process using SPEG technique is advantageous for production o f high speed bipolar LSIs.
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