A 100 k-gate ECL standard-cell LSI with layout system

Abstract

This ECL device achieves lOOk-gate integratiun with a standard cell layout approach, A standard·cell CAD architecture enables high-power ECL gate cells and freely placed megacells to be in· tegrated on a chip with fixed-pattern power supply buses. The 3"m.thick top (4th) metal layer is dedicated to the main power bnses.Under the main power buses are densely packed poly cells (polycell seas) and megacells surrounded by global chip routing channels and fixed-pitch sub· power buses, in the 3rd metal layer and orthogonal to the main power buses ( Figure 1). This structure gives the chip a density twice that of conven· tional ECL gate arrays and a more flexible layout without com promising high. power capacity.The die of the 60W chip is 14.72mm square, with lOOk equivalent gates and a maximum gate density of 1255 gates/mm'. This chip is mounted on the 56 I-pin PGA package with TAB leads and bumps on the die with 100"m pitch. (Figure 2) The thermal resistance Uunction.ambient) of the package is less than 10 C/W at an air flow of 10m/so Maximum dissipation in this package is 60W.A wafer process involves an emitter· base self-aligned struc· ture with polysilicon electrodes and resistors (ESPER), rom· bined with U·FOX isolation and four metal layers with a mini mum 2,6"m routing pitch'. Metal wires on 2nd metal layer and orthogonal 1st metal wires lying under 3rd metal sub-power buses form the global channels with a 2.6"m pitch uutside the polycell seas and megacells. In the polycell sea, the 2,6"m pitch 2nd metal wire; and the 5.2"m.pitch 3rd metal wires form inter· cell port routing over intra· cell transistor and resistor patterns on 1st metal layer.CAD lays out the chip with 2·level hierarchical steps.Step 1 is the chip floor plan using megacells and macro blocks consisting of logically connected polycells. The polyeell sea is assigned for the macro block and surrounded by the exclusive global channels. Megacells can be placed anywhere by CAD, the 3rd metal sub· power buses being substituted with ;lrd metal power supply pat· terns in their budy (Figure 3). External macroblock ports are planned for positioning at the periphery of the poly cell sea so that external connections of macroblocks use only the global channels. That is, routing inside macroblocks in step 2 is not affected by external connection wiring, which is nsually very long, and CAD produces a high.quality layout easily.This blocked poly cell sea reduces poly cell size more com· plr.tely than a conventional standard·cell or channel-less approach in which, with densely packed cells but no exclusive global chan· nels, each cell should have feed-through channels fur global can· nection only to pass through the cell. This approach does not have this layuut loss, and can have a density about twice that of the conventional approach with the same process technology. This is a 500/0 cut in cell size and an average 300/0 cut in wiring length (Figure 4). 94In the power bus scheme of Figure 1, the horizontal fixed main power buses (4th metal layer) and the vertical ...