Considerations of ultrahigh‐speed, low‐power active pull‐down NTL logic circuits

Abstract

Low‐power logic circuits are necessary in order to realize high‐integration, ultrahigh‐speed logic LSIs. For this purpose, a new circuit is proposed which adds an active pull‐down circuit to an NTL circuit with emitter follower which is a logic circuit with small logic swing of 500 mV. Compared to the conventional ECL circuit, this circuit achieves 2.75 times higher speed under 1 mW/gate power and an average wire capacitance of 0.57 pF per gate. As a result of fabricating this active pull‐down NTL logic circuit by 0.5 μm SICOS self‐aligned transistor with U‐groove, a minimum delay time of 25.3 ps, and the load drive capability of 50 ps/pF have been realized. Furthermore, this circuit can achieve even lower power with high speed by adding a pMOS transistor to the collector of input transistor. The simulation has shown that the circuit is four times faster compared to the conventional NTL circuit with an emitter follower with the same power consumption of 0.3 mW/gate and the load capacitance of 1 pF if a pMOS drain current of around 1 mA can be realized with conditions Vds, = ‐0.5 V and Vgs = ‐1.3 V.