A 12.5Gb/s CMOS BER test using a jitter-tolerant parallel CDR

Abstract

Pulse pattern generators (PPG) and bit error rate testers (BERT) are widely used in evaluating communications systems. Systems for telecommunications and data communications require various data rates ranging from 9.95 to 12.5Gb/s for testers, depending on encoding methods. For instance the 10 Gigabit small form factor pluggable module (XFP) specifications require 11.1Gb/s data rate with 0.45UIpp non-data-dependent jitter tolerance. This paper describes a CMOS LSI integrating PPG and BERT functions ( Fig. 9.5.1). A parallel CDR circuit allows the LSI to operate at a rate as high as 12.5Gb/s. It also provides wide jitter tolerance for high-frequency (4-80MHz) sinusoidal jitter.A CDR using linear phase detector (PD) [1] has many merits, including a jitter-transfer bandwidth independent of input-jitter amplitude, stable capture range, and quick loop design using classical control theory. However, a linear PD requires highspeed gates for up-pulse generation. The up-pulse width is reduced from T/2 (where T is the unit interval of input data) proportional to the phase error between data and clock. This limits the maximum operation rate of the CDR. The half-rate clock scheme [2] itself does not solve this problem. To extend up-pulse width, we use a parallel phase detector (P-PD) and two chargepump (CP) circuits in a double-loop architecture CDR ( Fig. 9.5.2). The P-PD separately compares the phase error between the odd-number data-transition edge and half-rate-clock rising edge, and the phase error between the even-number data-transition edge and half-rate-clock falling edge. The two CP outputs are commonly connected to a low-pass filter for detection of the whole data transition so as to eliminate the data-pattern dependency.The P-PD is shown in Fig. 9.5.3. It compares odd-and evennumber-data edge and half-rate clock edge in parallel. Latch-2 passes through the odd-number data-transition edge and outputs even-number data with the rising edge of a half-rate clock. Latch-3 outputs even-number data using the half-rate-clock rising edge. Thus, the pulse width of the Exor_1 output (Up_1) is the time between the odd-number data-transition edge and halfrate-clock rising edge. The Up_2 pulse is made in the same manner from the even-number data-transition edge and half-rateclock falling edge. As a result, the width of the up-pulse output from this P-PD is 1.25T ± T/2, which is longer than the conventional up-pulse width of T/2 ± T/2, where T is a unit interval of data and ±T/2 is the variation of the time between the data-transition edge and clock-transition edge due to input data jitter.An XOR gate made with low-f T transistors eliminates the narrow up-pulse due to the slow rise/fall time; however, when the pulse is wide, it can accurately output the width difference of the uppulse. Therefore the parallel phase detector has a wide linear response to large phase error. As shown in Fig. 9.5.4, a backannotated simulation at 11.1Gb/s indicates that the P-PD improves the linear response range to phase error from 0.33 to 0.56UI, su...

A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector

“…This leads to the VCO control voltage having little activity, which in turn translates to lower in-lock jitter [3]. Secondly, a CDR circuit using a linear phase detector has a jitter-transfer bandwidth which is independent of the amplitude of the input jitter [4]. Thirdly, a linear phase detector is intrinsically tri-stated, which is important to meeting jitter generation specifications.…”

“…Using this fact with (1) and (2), the probability of an error can be calculated as (3) The integral in (3) cannot be solved directly, however, the Q-function can be used to make the analysis easier to work with. It is important to remember that the probability of an error is equal to the BER and hence using the Q-function with (3) the BER can be written as (4) A static phase offset in a CDR circuit moves the sampling point away from the center of the data eye. In a mathematical analysis this has the effect of moving the mean of the Gaussian distribution by the amount of the static phase offset.…”

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

“…CDR ARCHITECTURE To meet both jitter transfer and jitter tolerance requirements, the linear CDR circuits are widely used [2], [3], [7]. Let the phase of input data modulated by sinusoidal jitter and that of the recovered clock for a linear CDR circuit be and , respectively.…”

“…Hence, enhancing the jitter tolerance by only increasing the loop bandwidth degrades the jitter transfer and may not be accepted for some applications such as data repeaters [1]. In traditional optical receivers [2], [3] without jitter tolerance enhancement, the jitter tolerance at higher jitter frequency (tens of MHz) is hard to exceed 0.5 UIpp (UI: unit interval). One of the remedies is to adopt the analog phase shifter such as a delay-locked loop (DLL) [4], [5].…”

Analysis of bang-bang clock and data recovery

“…Both the setup/hold times and process speed are the limiting factor to realize high speed CDR using a linear phase detector. Alternative techniques for utilizing a high speed CDR using a linear phase detector are reported [17], [18].…”