A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

Abstract

A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 m CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 mm 2 . The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 2 7 1 PRBS. The measured bit error rate for a 10 Gb/s 2 7 1 PRBS is less than 10 12 .

An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

“…This situation should be considered as an ERROR case. Therefore, probabilities of (6), (7), and (9) should be considered to derive the BER. The probabilities that two adjacent data edges are located as (6), (7), and (9) Assume all events are independent, and the product events, the probability of satisfying (6), (7), and (9) is P data,sum (a, σ data ) = P data,left (x < a, σ data ) × P data,right (y < a, σ data ) + P data,left (x > a, σ data ) × P data,right (y > a, σ data ) + P data,left (x > a, σ data ) × P data,right (y < a, σ data ).…”

“…The BER with quantized phase alignment can be expected to have a better BER performance than (13). The summation of product probability of (15) and (16) based on error conditions (6), (7), and (9) is P data,sum,prac (a, σ data ) = P data,left,prac (x < a, σ data ) × P data,right,prac (y < a, σ data ) + P data,left,prac (x > a, σ data ) × P data,right,prac (y > a, σ data ) + P data,left,prac (x > a, σ data ) × P data,right,prac (y < a, σ data ).…”

A PLL/DLL based CDR with &#x0394;&#x03A3; frequency tracking and low algorithmic jitter generation

“…However, the PLL based CDR system has difficulty in overcoming the fundamental trade off between the jitter transfer and the jitter tolerance since both properties depends on the PLL bandwidth. There have been several architectures proposed to achieve the independent bandwidth control in the literature [1]- [4]. The delay-and phase-locked loop (D/PLL) based CDR system, as shown in Fig.…”

“…1, offers an elegant way of realizing a type-II feedback system without jitter peaking and enables different corner frequencies of the jitter transfer and the jitter tolerance [1]- [2]. The cascaded PLL-DLL architecture provides more straightforward way of achieving independent control but hardware complexity as well as loop filter area increases substantially [3], and the use of the gated DCO further simplifies the cascaded architecture [4]. Compared to the conventional PLL based CDR system, the D/PLL or PLL-DLL based CDR system requires additional PVT-sensitive analog building blocks.…”

A 10Gb/s wire-line transceiver with half rate period calibration CDR

“…To avoid that the offchip communication becomes the bottleneck of the overall system performance, the off-chip bandwidth grows increasingly [1], [2]. Moreover, to meet the increasing performance demand of new applications, it is not only need higher bandwidth but also gradually care about the power efficiency of the chip-to-chip communication [3], [4].…”