A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing

Takaya, Satoshi; Nagata, Makoto; Sakai, Atsushi; Kariya, Takashi; Uchiyama, S.; Kobayashi, H.; Ikeda, Hiroaki

doi:10.1109/isscc.2013.6487803

Cited by 42 publications

(20 citation statements)

References 5 publications

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“…This option has initially attracted the most attention and research and development efforts; many prototypes and products nowadays are based on TSV technology [2], [5], [6], [18], [28], [29], [30], [31]. The key element, the through-silicon vias (TSVs) are metal plugs (typically copper or tungsten) that penetrate whole stacked dies in order to interconnect those dies.…”

Section: Tsv-based 3d Icsmentioning

confidence: 99%

“…Interposer stacks are a widely accepted, cost-efficient alternative to 3D ICs [8], [16], [17], [18], [19], [20], [21], [22]. Here, active dies are arranged in lateral direction on a substrate-possibly on both of its sides-instead of stacking them strictly vertically.…”

Section: Interposer Stacksmentioning

confidence: 99%

“…A key observation is that most challenges can be eased once system-level 3D integration (of 2D chips) is pursued. The related concept of interposer-based 3D integration is widely accepted nowadays [8], [16], [17], [18], [19], [20], [21], [22]; it is a practical, flexible, and cost-effective alternative to the previously more anticipated full-custom and native 3D integration.…”

Section: Introductionmentioning

confidence: 99%

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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Section: Tsv-based 3d Icsmentioning

confidence: 99%

Section: Interposer Stacksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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“…The entire 3D chip stack including the organic substrate is plastic molded and assembled on a system printed circuit board (PCB) for performance evaluation. As one of the first demonstrators of wide bandwidth vertical signaling, a wide input/output bus was embodied in the structure with 4096-bit TSV data channels and accomplished the power efficiency of 0.56 mW/Gb/s with 1.2 V power supply, at the data transfer of 100 GByte/s [6].…”

Section: Wide I/o Test Vehiclementioning

confidence: 99%

“…The selection of driving current in mini I/O circuits (Fig. 8) was demonstrated in [6], where the in-place waveforms were characterized in eye opening as the measure of stable signaling. The completeness of 3D process technologies is also indirectly proven by the stable waveforms.…”

Section: Signal and Power Integritymentioning

confidence: 99%

Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking

Takaya

Ikeda

Nagata

2014

IEICE Trans. Electron.

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Satoshi TAKAYA†a) , Student Member, Hiroaki IKEDA †b) , Nonmember, and Makoto NAGATA †c) , Senior Member SUMMARY A three dimensional (3D) chip stack featuring a 4096-bit wide I/O demonstrator incorporates an in-place waveform capturer on an intermediate interposer within the stack. The capturer includes probing channels on paths of signaling as well as in power delivery and collects analog waveforms for diagnosing circuits within 3D integration. The collection of in-place waveforms on vertical channels with through silicon vias (TSVs) are demonstrated among 128 vertical I/O channels distributed in 8 banks in a 9.9 mm × 9.9 mm die area. The analog waveforms confirm a full 1.2-V swing of signaling at the maximum data transmission bandwidth of 100 GByte/sec with sufficiently small deviations of signal skews and slews among the vertical channels. In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75 V for error free data transfer at 100 GByte/sec, achieving the energy efficiency of 0.21 pJ/bit. key words: wide I/O bus, through silicon via, signal integrity, power integrity

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3D Stacking of RAM–Processor Chips Using TSV

2014

Vertical 3D Memory Technologies

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A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing

Cited by 42 publications

References 5 publications

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking

3D Stacking of RAM–Processor Chips Using TSV

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