Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking

Abstract

Satoshi TAKAYA†a) , Student Member, Hiroaki IKEDA †b) , Nonmember, and Makoto NAGATA †c) , Senior Member SUMMARY A three dimensional (3D) chip stack featuring a 4096-bit wide I/O demonstrator incorporates an in-place waveform capturer on an intermediate interposer within the stack. The capturer includes probing channels on paths of signaling as well as in power delivery and collects analog waveforms for diagnosing circuits within 3D integration. The collection of in-place waveforms on vertical channels with through silicon vias (TSVs) are demonstrated among 128 vertical I/O channels distributed in 8 banks in a 9.9 mm × 9.9 mm die area. The analog waveforms confirm a full 1.2-V swing of signaling at the maximum data transmission bandwidth of 100 GByte/sec with sufficiently small deviations of signal skews and slews among the vertical channels. In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75 V for error free data transfer at 100 GByte/sec, achieving the energy efficiency of 0.21 pJ/bit. key words: wide I/O bus, through silicon via, signal integrity, power integrity

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A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus

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