Abstract:This paper describes theoretical approach and proposed scheme of wide data bus architecture using charge-recycling and stacked I/O for signal transmission via TSV (Through Silicon Via). This data bus is assumed for vertical stacked chips of 3D integration. This theoretical approach is based on probability calculation for data stream on pure random pattern. Through the calculation, power reduction ratio to normal data bus (non-charge recycling) is clarified in given conditions for power estimation in early desi… Show more
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