Landside capacitor efficacy among multi-chip-module using Si-interposer

Araga, Yuuki; Kasai, Ryo; Tanaka, Daichi; Murakami, Yoshihide; Mihara, Kyoshi; Makida, Kazuo; Sonoda, Hiroki; Nagata, Makoto; Watanabe, Naoya; Shimamoto, H.; Kikuchi, Katsuya

doi:10.1587/elex.18.20210070

Cited by 2 publications

(3 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The OCM circuits includes probing front end (PFE) modules for sensing individual analog voltage signals at respective probe inputs and a data processing unit (DPU) for digitizing voltage waveforms after a multiplexer (MUX) [29], [30]. The PFE module of OCM system, Fig.…”

Section: B MCM Demonstrator With Test Ic Chipmentioning

confidence: 99%

“…The benefits of embedded capacitors in FOWLP devices were also exhibited by monitoring power and signal waveforms [27], [28]. The implications with the different property of interposers have been relevantly discussed with the same device architecture but integrated on a Si passive interposer differently from the fan-out one, which should be referred to [29]. Here, our demonstration was self-explanatory but limited only to qualitative observations in the previous reports, which were insufficient to discuss the selection of capacitors in the design of a PDN.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Sonoda

Kasai

Tanaka

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

Self Cite

View full text Add to dashboard Cite

This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based builtin self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs.

show abstract

Section: B MCM Demonstrator With Test Ic Chipmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Sonoda

Kasai

Tanaka

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Through-silicon via (TSV) based three-dimensional integrated circuit (3D IC) provides many benefits over traditional interconnection such as abundant interconnect bandwidth, less communication energy, reduced power consumption and improved performance [1]. It is also widely used in filter [2,3,4,5,6] and passive devices [7,8,9,10,11,12].…”

Section: Introductionmentioning

confidence: 99%

Wideband transmission optimization for heterogenous interconnection in 3D IC

Yin

Wang

2022

IEICE Electron. Express

View full text Add to dashboard Cite

Through-silicon via (TSV) is proved to have great potential in high density, high performance integrated circuit. This work aims at reducing the loss of heterogeneous interconnection in three-dimensional integrated circuit (3D IC). The equivalent circuit models of TSV and redistribution layer (RDL) are established, they are in good agreement with finite element method (FEM) simulation results. An optimized structure with capacitive element is proposed to improve the transmission in heterogenous interconnection. The simulation indicates great transmission improvement at wide band from DC to 70 GHz.

show abstract

Landside capacitor efficacy among multi-chip-module using Si-interposer

Cited by 2 publications

References 29 publications

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Wideband transmission optimization for heterogenous interconnection in 3D IC

Contact Info

Product

Resources

About