A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems

Scheytt, J. Christoph; Hanke, G.; Langmann, U.

doi:10.1109/4.808918

Cited by 17 publications

(8 citation statements)

References 6 publications

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“…Due to the limited lock range, the correct frequency must be acquired before phase locking. Conventional dual-loop architecture [12], [13] requires a local frequency reference. Some referenceless approaches such as Pottbacker frequency detector can avoid the need for a reference by using quadrature clocks to distill the frequency information.…”

Section: B Frequency Acquisitionmentioning

confidence: 99%

“…Redrawing the latch with peaking inductor and the equivalent model in regeneration mode [ Fig. 13(b)], we calculate the output ( ) again: (12) For the most flat response [the damping factor ], we obtain an explicit solution for , which grows up exponentially with a new time constant : 3 (13) As compared with , the positive-feedback process is accelerated by a factor of (14) Note that must be greater than unity to guarantee positive feedback. Fig.…”

Section: B Retiming Flipflopmentioning

confidence: 99%

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A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition

Lee

2009

IEEE J. Solid-State Circuits

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A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data phases rather than the clock phases to distill the frequency difference, and no external reference is used in this design. Fabricated in 90-nm CMOS technology, this circuit reveals rms and peak-to-peak jitter of 480 fs and 4.22 ps in response to a 2 31 1 PRBS on the recovered clock while consuming 154 mW from a 1.5-V supply.

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Section: B Frequency Acquisitionmentioning

confidence: 99%

Section: B Retiming Flipflopmentioning

confidence: 99%

A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition

Lee

2009

IEEE J. Solid-State Circuits

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“…A CDR architecture utilizing such a scheme is shown in Fig. 7a [8]. Here, loop I phase-locks VCO 1 to the input data through fine control.…”

Section: Architectures With External Referencesmentioning

confidence: 99%

Challenges in the design high-speed clock and data recovery circuits

2002

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This article describes the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of phase detection for random data is addressed. Next, Hogge, Alexander, and half-rate phase detectors are introduced and their trade-offs outlined. Finally, a number of clock and data recovery architectures are presented.

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“…For wide-range CDR, two kinds of circuit schemes have been researched. One is the multirate CDR circuit with multiple reference clocks [2] or single reference clock with a programmable divider [3] or without reference clock [4,5]. The other is the continuous-rate CDR circuit with fractional-N divider [6] or without an external reference clock [7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%