A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition

Abstract

A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data phases rather than the clock phases to distill the frequency difference, and no external reference is used in this design. Fabricated in 90-nm CMOS technology, this circuit reveals rms and peak-to-peak jitter of 480 fs and 4.22 ps in response to a 2 31 1 PRBS on the recovered clock while consuming 154 mW from a 1.5-V supply.

A 20 Gb/s Injection-Locked Clock and Data Recovery Circuit

“…The output frequency of the oscillator is divided by 40 and then is applied to a frequency detector. The frequency detector circuit is shown in Figure. 2 which is a rotational frequency detector circuit [10]. It compares the divider output frequency with a reference frequency of 250 MHz and produces an up/down signal and a clock for the counter.…”

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

“…The referenceless CDR satisfies this requirement. The referenceless CDR [3][4][5][6][7][8][9][10][11][12][13][14][15][16] extracts the clock signal from the received data signal alone without using any reference clock sources ( Fig. 1(b)).…”

“…One solution to this problem is to limit the output frequency of the voltage-controlled oscillator (VCO) in the referenceless CDR to within ± 50 % of the target frequency [3][4][5][6][7]. However, this restriction limits the usable range of input data rate to a narrow range.…”

8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS

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As an alternative to the conventional dual-loop architecture, reference-less CDR architectures have become more popular in industry because of their simplicity and flexibility [1][2][3][4][5]. However, the robustness of the transition between frequency acquisition and phase locking is always a concern, particularly for the linear CDR, which has an extremely limited capture range.

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“…Many works, based mainly on the Pottbacker frequency detector (FD) [1], have been reported. In [3] the capture range of the FD is only ±2.4% at 20Gb/s with no capacitor bank in the VCO; in [4] the capture range of the FD is about ±6.4% at 2.75Gb/s, with an 8b resolution of the capacitor bank in the VCO; in [5] the capture range is ±15% at 10Gb/s, with an 11b resolution of the capacitor bank. Thus the Pottbacker FD inherently suffers from a limited capture range, requiring a dedicated FD and a stringent tradeoff between the CDR capture range and the number of VCO bands.…”