Challenges in the design high-speed clock and data recovery circuits

Abstract

This article describes the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of phase detection for random data is addressed. Next, Hogge, Alexander, and half-rate phase detectors are introduced and their trade-offs outlined. Finally, a number of clock and data recovery architectures are presented.

Statistical Analysis of First-Order Bang-Bang Phase-Locked Loops Using Sign-Dependent Random-Walk Theory

“…The average time (phase) difference between the two clocks in the locked state is the static timing offset (static phase error). A static timing offset is a significant problem in a BBPLL-based CDR circuit because it results in the incoming data no longer being sampled at the center of the data eye, thus increasing the bit error rate [3].…”

“…The distinct feature of BBPLLs is the binary phase detector (BPD) which binary quantizes the phase difference between input data and voltage-controlled oscillator (VCO) clock, generating only early/late phase-error information for the loop filter (LF). To suppress patterndependent jitter in a CDR application, the BPD is usually a tristate realization such as the Alexander topology [3]. BBPLLs have also been demonstrated for high-bandwidth digital frequency synthesis [4], [5].…”

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

“…This clock has to be recovered at the receiver side in order to sample and process the received data. Therefore, a Clock and Data Recovery (CDR) circuit is an essential component in such a high speed receiver, and the design and the performance of the CDR has a significant influence on the overall operation of the link [1].…”

A CMOS Ripple Detector for Voltage Regulator Testing

“…Supply ripple can have detrimental effects on the performance of various blocks in an SOC including but not limited to; noise and distortion in analog circuits [6,9], conversion errors in high performance analog to digital converters [9], and jitter in high speed clock and data recovery circuits [14]. Hence, low supply ripple is crucial for all types of circuits and testing of PMUs in terms of ripple is significant.…”