A 0.026mm&lt;sup&gt;2&lt;/sup&gt; 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter

Jang, Taekwang; Xing, Nan; Liu, F.; Shin, Jungeun; Ryu, Hyungreal; Kim, Jihyun; Kim, Tae-Ik; Park, Jaejin; Park, Ho‐Jin

doi:10.1109/isscc.2013.6487723

Cited by 12 publications

(2 citation statements)

References 7 publications

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“…Instead, if the two terms become comparable, the random noise dithers the periodic quantization error, and the simulated level of spurs is slightly lower than the theoretical value. Nevertheless, this analysis confirms that the level of fractional spurs in a DPLL strongly depends on the resolution of the TDC [4], [16], and this fact justifies the need for a high-resolution TDC in a fractional-N DPLL [17]- [20].…”

Section: A Conventional Digital Pllssupporting

confidence: 61%

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

Levantino

Marzin²,

Samori

2014

IEEE J. Solid-State Circuits

103

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Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multi-bit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power con- sumption of 4.2 mW

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Section: A Conventional Digital Pllssupporting

confidence: 61%

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

Levantino

Marzin²,

Samori

2014

IEEE J. Solid-State Circuits

103

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“…An attractive method uses hybrid loops to achieve low jitter PLLs [18,19,20], as well as results in rather complicated circuits. More and more digital PLLs [21,22,23,24,25,26] are designed due to the advantages in terms of power, area, and programmability, whereas the improvement is needed in the jitter performance of digital PLLs. The Ring-VCO is the most important component of the PLL, in which the low phase noise and wideband characteristics directly determine the jitter and frequency range of PLLs.…”

Section: Introductionmentioning

confidence: 99%

A wideband low-jitter PLL with an optimized Ring-VCO

Zou

Ren

Zou

2020

IEICE Electron. Express

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A wideband low-jitter phase-locked loop (PLL) is proposed to provide high performance clocks for the transceivers. The ring voltagecontrolled oscillator (Ring-VCO) is a key component of a PLL, which directly determine the out-band phase noise and output frequency range of the PLL. Therefore, a low phase noise two-stage Ring-VCO with a novel delay cell is proposed to help achieve a wideband low-jitter PLL. An accumulation-mode MOS (AMOS) varactor pair is adopted in the delay cell to improve the fine tuning linearity. Moreover, an additional AMOS varactor pair is employed to reduce the VCO gain variation in the coarse tuning process and enhance the tolerance in temperature and voltage variations. Implemented in a conventional TSMC 180 nm CMOS process, the proposed Ring-VCO can tune from 0.73 to 1.92 GHz and the worstcase phase noise at 1 MHz offset is −102 dBc/Hz. The output frequency range of the proposed PLL is 0.06-1.92 GHz and the RMS jitter is less than 3.8 ps over the whole working band.

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Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL

Liu,

Yang,

Wang

et al. 2024

Microelectronics Journal

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A 0.026mm<sup>2</sup> 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter

Cited by 12 publications

References 7 publications

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

A wideband low-jitter PLL with an optimized Ring-VCO

Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL

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