A wideband low-jitter phase-locked loop (PLL) is proposed to provide high performance clocks for the transceivers. The ring voltagecontrolled oscillator (Ring-VCO) is a key component of a PLL, which directly determine the out-band phase noise and output frequency range of the PLL. Therefore, a low phase noise two-stage Ring-VCO with a novel delay cell is proposed to help achieve a wideband low-jitter PLL. An accumulation-mode MOS (AMOS) varactor pair is adopted in the delay cell to improve the fine tuning linearity. Moreover, an additional AMOS varactor pair is employed to reduce the VCO gain variation in the coarse tuning process and enhance the tolerance in temperature and voltage variations. Implemented in a conventional TSMC 180 nm CMOS process, the proposed Ring-VCO can tune from 0.73 to 1.92 GHz and the worstcase phase noise at 1 MHz offset is −102 dBc/Hz. The output frequency range of the proposed PLL is 0.06-1.92 GHz and the RMS jitter is less than 3.8 ps over the whole working band.
Due to the high parallelism, Data flow architecture is a common solution for deep neural network (DNN) acceleration, however, existing DNN accelerate solutions exhibit limited flexibility to diverse network models. This paper presents a novel reconfigurable architecture as DNN accelerate solution, which consists of circuit blocks all can be reconfigured to adapt to different networks, and maintain high throughput. The proposed architecture shows good transferability to diverse DNN models due to its reconfigurable processing element (PE) array, which can be adjusted to deal with various filter sizes of networks. In the meanwhile, according to proposed data reuse technique based on parameter proportion property of different layers in DNN, a reconfigurable on-chip buffer mechanism is raised. Moreover, the accelerator enhances its performance by exploiting the sparsity property of input feature map. Compared to other state-of-the-art solutions based on FPGA, our architecture achieves high performance, and presents good flexibility in the meantime.
The adaptive bias technique is the common technology for improving the power-added efficiency (PAE) of the power amplifier (PA). However, the performance of the adaptive bias technique is sensitive to the frequency variation. This paper presents a novel adaptive bias as the common-source bias of the 45-2500 MHz CMOS PA, which combines the subthreshold PD to decrease the effect on frequency of adaptive bias technique and a unity gain amplifier to increase the detection sensitivity, for improving the PAE at back-off mode over the wide bandwidth. The proposed PA provides a good performance from 45 MHz to 2500 MHz, while the peak of the saturation output power is 24.02 dBm over the frequency band. Moreover, the maximum PAE achieves 44.61 % at 500 MHz and the PAE is larger than 28.48 % at 3 dB back-off power. The chip size of the broadband PA achieves 1.87 mm 2 at TSMC 0.18 um technology process. It draws 200 mA from 3.3 V supply voltage.
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