An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

Abstract

Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multi-bit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power con- sumption of 4.2 mW

Fractional spur suppression in all-digital phase-locked loops

“…In each part, the correlation between the detected phase error and 1 − P HR F still exists. What's more, there is another correlation relationship in each piece of the P HR F , as described in [7]. That makes it practical to calibrate DTC gain with four segments.…”

“…In another ADPLL [7], a single-bit TDC and two-stages of DTCs are chosen. A coarse stage and a fine stage DTC follow the integer divider of the oscillator clock.…”

“…However, such calibration is quite straightforward and could be done entirely in the digital domain. Recent ADPLL architectural improvements replace the TDC with a digital-to-time converter (DTC) [4] and a combination of DTC and TDC [5] [6] [7] .…”

Digitally Assisted Analog and RF Circuits

“…The PLLs [39], [40] still need special custom cells for layout synthesis. At the present implementation, the jitter performance is degraded by the non-linearity of TDC while it can be potentially improved by the calibration techniques [30].…”

“…The recent AD-PLL sometimes uses DTC as well as TDC, and TDC and DTC usually have gain mismatch and non-linearity. Fortunately, the mismatch and non-linearity can be easily calibrated and compensated [30], and a background calibration is also possible. This is very important advantage of AD-PLL.…”