600 V -Class V-Groove SiC MOSFETs

Saitoh, Y.; Furumai, Masaki; Hiyoshi, Toru; Wãda, Keiji; Masuda, Takuro; Hiratsuka, Kenji; Mikamura, Yasuki; Hatayama, Tomoaki

doi:10.4028/www.scientific.net/msf.778-780.931

Cited by 13 publications

(7 citation statements)

References 4 publications

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“…Gate stacks consist of poly-Si and thermal SiO 2 . In order to reduce the parasitic resistance, source and drain (S/D) were elevated by Si-epi growth with thin sidewall spacer of 10 nm [3]. The key technique for fabricating UTBT NW Tr.…”

Section: Fabrication Of Utbt Nw Trmentioning

confidence: 99%

Systematic Study of Back-Gate Bias Effects in Ultrathin-BOX Tri-gate (UTBT) Transistor with 10nm-Diameter Nanowire Channel

Ota

Saitoh

Tanaka

et al. 2012

Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials

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Section: Fabrication Of Utbt Nw Trmentioning

confidence: 99%

Systematic Study of Back-Gate Bias Effects in Ultrathin-BOX Tri-gate (UTBT) Transistor with 10nm-Diameter Nanowire Channel

Ota

Saitoh

Tanaka

et al. 2012

Extended Abstracts of the 2012 International Conference on Solid State Devices and Materials

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“…The VMOSFET with the buried p + regions demonstrates the blocking capability of 1700 V as an avalanche breakdown at room temperature. Conversely, a blocking voltage for the VMOSFET without the buried p + regions is 575 V, generating the gate-oxide breakage at the trench bottom [19]. The measured high-blocking voltage can be obtained by the buried p + regions alleviating the electric field crowding at the trench bottom.…”

Section: B Experimental Results and Discussionmentioning

confidence: 99%

Novel Designed SiC Devices for High Power and High Efficiency Systems

Mikamura

Hiratsuka

Tsuno

et al. 2015

IEEE Trans. Electron Devices

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Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (D it ) of 3 × 10 11 cm −2 eV −1 , which causes the high channel mobility of 80 cm 2 V −1 s −1 results in very low channel resistance. The buried p + regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 m cm 2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 m cm 2 and the blocking voltage of 3850 V are obtained for 3300 V application. Index Terms-(0-33-8) face, 4H-silicon carbide (SiC), buried p + region, channel mobility, field-limiting ring (FLR), junction FET (JFET), junction termination extension (JTE), MOSFET, V-groove trench.Yasuki Mikamura received the B.E. and M.E. degrees in electrical engineering from Kyoto University, Kyoto, Japan, in 1983 and 1985, respectively.

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“…The structure with a P + region under the bottom of the SiC gate trench was proposed to shield the gate oxide in 2002 [6], but it reduces the on‐current of the device due to the parasitic JFET formed between the P ‐base and the P ‐bottom. Although a thick bottom gate oxide also can decrease the electric field in the gate oxide, the thick bottom must be achieved by a V ‐groove gate design and the effect of restraining electric field is dependent on etching and lithography accuracy [7].…”

Section: Introductionmentioning

confidence: 99%

Investigation of SiC trench MOSFET with floating islands

Song

Tang

Zhang

et al. 2016

IET Power Electronics

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The silicon carbide trench metal-oxide-semiconductor field-effect transistors (SiC UMOSFET) with P + floating island (FLI) which shields the gate oxide at the bottom of the gate trench from the high electric field during the blocking state and enhances the breakdown voltage (BV), is presented in this study using two-dimensional simulations. The effects of doping concentration, length and position of FLI on BV, electric field distribution and specific on-resistance (R on,sp) are studied, thereby providing particularly useful guidelines for the design of this new type of device when considering the breakdown of the gate oxide layer. For the suitable device design, the results indicate that BV and Baliga figure of merit are, respectively, increased by 150 and 439% compared with a conventional SiC UMOSFET. At the same time, the SiC FLI UMOSFET has smaller gate-drain capacitance and better switching performance compared with the conventional UMOSFET on the condition of the same drift layer parameters. FLI introduced have almost no influence on the recovery characteristics of body diode.

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600 V -Class V-Groove SiC MOSFETs

Cited by 13 publications

References 4 publications

Systematic Study of Back-Gate Bias Effects in Ultrathin-BOX Tri-gate (UTBT) Transistor with 10nm-Diameter Nanowire Channel

Systematic Study of Back-Gate Bias Effects in Ultrathin-BOX Tri-gate (UTBT) Transistor with 10nm-Diameter Nanowire Channel

Novel Designed SiC Devices for High Power and High Efficiency Systems

Investigation of SiC trench MOSFET with floating islands

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