Novel Designed SiC Devices for High Power and High Efficiency Systems

Abstract

Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (D it ) of 3 × 10 11 cm −2 eV −1 , which causes the high channel mobility of 80 cm 2 V −1 s −1 results in very low channel resistance. The buried p + regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 m cm 2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 m cm 2 and the blocking voltage of 3850 V are obtained for 3300 V application. Index Terms-(0-33-8) face, 4H-silicon carbide (SiC), buried p + region, channel mobility, field-limiting ring (FLR), junction FET (JFET), junction termination extension (JTE), MOSFET, V-groove trench.Yasuki Mikamura received the B.E. and M.E. degrees in electrical engineering from Kyoto University, Kyoto, Japan, in 1983 and 1985, respectively.

Flexible Transparent and Free‐Standing SiC Nanowires Fabric: Stretchable UV Absorber and Fast‐Response UV‐A Detector

“…The nanowire quality stands alongside the self‐assembly of the nanowire fabric as another stubborn difficulty, because the occurrence of complex planar stacking faults (SFs) is a ubiquitous and uncontrollable event . This feature and the indirect nature of their bandgap mean that SiC nanowires are seldom applied for photonic purposes because of the screening effects of phonon processes, despite their many advantages, including being well suited to high‐frequency, high‐power, and high‐temperature devices, and possessing anticorrosion and radio resistance properties . We here demonstrate the self‐assembly of 2H‐SiC FTS‐NWsF using airflow‐oriented growth to form a nanowire network, and the elimination of dense planar SFs by the introduction of Al and O dopants.…”

A New SiC Planar-Gate IGBT for Injection Enhancement Effect and Low Oxide Field

“…A feasible fabrication procedure of the new SiC IGBT is proposed with a set of established process steps in conventional planar gate SiC IGBT [12,[41][42][43]. The proposed fabrication flow is illustrated in Figure 10.…”

“…All the implantation should be followed by high-temperature annealing in argon gas. Then, an n-type SiC layer is regrown [42,43], following which, the p-body regions and n+ regions are formed by ion implantations. Then, the trenches are created by dry etching, followed by gate oxide growth or deposition.…”

SiC trench MOSFET with self‐biased p‐shield for low R ON‐SP and low OFF‐state oxide field

“…However, a high electric field (E-field) in the gate oxide can be easily created at the bottom or corners of the trench when the device is biased at the high-voltage OFF-state. This high peak E-field in the gate oxide could accelerate the gate oxide failure, resulting in degraded device reliability [11][12][13]. An effective approach to reducing the maximum oxide field (E ox-m ) to a safe level (<3 MV/cm) is to introduce a grounded p-shield region under the gate trench [13][14][15].…”