6.5 V High Threshold Voltage AlGaN/GaN Power Metal-Insulator-Semiconductor High Electron Mobility Transistor Using Multilayer Fluorinated Gate Stack

Wang, Yun-Hsiang; Liang, Yung C.; Samudra, Ganesh S.; Huang, Huolin; Huang, Bo-Jhang; Huang, Szu-Han; Chang, Tsin‐Yuan; Huang, Chih-Fang; Kuo, Wei-Hung; Lo, Guo‐Qiang

doi:10.1109/led.2015.2401736

Cited by 50 publications

(16 citation statements)

References 10 publications

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“…Moreover, the MOS-gate is compatible with the mainstream gate driver ICs. However, the traps (e.g., interface and bulk traps) tarnish the advantages of GaN HFETs due to the stability and reliability issues such as V TH instability [ 9 ], drain lag or gate lag [ 10 ], and power slump. Besides the surface/interface traps, the GaN power HFETs’ performance such as the breakdown voltage and dynamic on-resistance could be substantially affected by the bulk traps in GaN buffer layer in high-voltage-switching applications [ 11 , 12 ] since the high electric-field is prone to trigger the buffer traps for dynamic charging/discharging.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Bulk Traps by Conductance Method in the Deep Depletion Region of the Al2O3/GaN MOS Device

et al. 2017

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Conductance method was employed to study the physics of traps (e.g., interface and bulk traps) in the Al2O3/GaN MOS devices. By featuring only one single peak in the parallel conductance (G p/ω) characteristics in the deep depletion region, one single-level bulk trap (E C-0.53 eV) uniformly distributed in GaN buffer was identified. While in the subthreshold region, the interface traps with continuous energy of E C-0.4~0.57 eV and density of 0.6~1.6 × 1012 cm−2 were extracted from the commonly observed multiple G p/ω peaks. This methodology can be used to investigate the traps in GaN buffer and facilitates making the distinction between bulk and interface traps.

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Section: Introductionmentioning

confidence: 99%

Investigation of Bulk Traps by Conductance Method in the Deep Depletion Region of the Al2O3/GaN MOS Device

et al. 2017

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“…where n and p refer to the concentration of electrons and holes, respectively, v n and v p refer to the saturation velocity of the electrons and the holes, respectively, and α n and α p are the values of the impact-ionization coefficient which relates to the electric field, and they are defined by Equation (2). The temperature dependence of the phonon gas against which carriers are accelerated is expressed by parameters γ n and γ p .…”

Section: Structures and Simulationmentioning

confidence: 99%

“…In (2), coefficients a n , a p , b n , and b p are fitting parameters, and their values are listed in Table 2 [25], [43].…”

Section: Structures and Simulationmentioning

confidence: 99%

Technology Computer Aided Design Study of GaN MISFET With Double P-Buried Layers

et al. 2019

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In this paper, a performance-improved AlGaN-/GaN-Based metal-insulator-semiconductor field effect transistor (MISFET) with double P-buried layers MISFET (DP-MISFET) is proposed. The proposed structure is simulated, and its characteristics are analyzed by the Sentaurus TCAD tool; the results show that with a gate-drain spacing of 6 µm, the optimized DP-MISFET can achieve high Baliga's figure of merit of 3.23 GW • cm −2 due to the modulation of the electric field distribution. Compared with the conventional MISFET (C-MISFET) with the breakdown voltage (BV) of 503.9 V and specific on-resistance (R on,sp ) of 0.63 m • cm 2 , the proposed structure can achieve a better trade-off between the breakdown voltage and specific on-resistance achieving R on,sp and BV of 0.63 m • cm 2 and 1427 V, respectively.

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“…However, there are still several important issues unaddressed, among which, the normally-off operation with a large threshold voltage (V th ) is a big concern when the chip products are pushed toward the market [8][9][10]. Several device architectures, such as p-GaN cap, barrier layer-recessed, fluorinated-gate, and cascode-connected metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs), have been reported to shift the threshold voltage to be positive [11][12][13][14][15][16]. Indeed, the device performances have been improved significantly in the past ten years.…”

Section: Introductionmentioning

confidence: 99%

A Novel GaN Metal-Insulator-Semiconductor High Electron Mobility Transistor Featuring Vertical Gate Structure

et al. 2019

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A novel structure scheme by transposing the gate channel orientation from a long horizontal one to a short vertical one is proposed and verified by technology computer-aided design (TCAD) simulations to achieve GaN-based normally-off high electron mobility transistors (HEMTs) with reduced on-resistance and improved threshold voltage. The proposed devices exhibit high threshold voltage of 3.1 V, high peak transconductance of 213 mS, and much lower on-resistance of 0.53 mΩ·cm2 while displaying better off-state characteristics owing to more uniform electric field distribution around the recessed gate edge in comparison to the conventional lateral HEMTs. The proposed scheme provides a new technical approach to realize high-performance normally-off HEMTs.

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6.5 V High Threshold Voltage AlGaN/GaN Power Metal-Insulator-Semiconductor High Electron Mobility Transistor Using Multilayer Fluorinated Gate Stack

Cited by 50 publications

References 10 publications

Investigation of Bulk Traps by Conductance Method in the Deep Depletion Region of the Al2O3/GaN MOS Device

Investigation of Bulk Traps by Conductance Method in the Deep Depletion Region of the Al2O3/GaN MOS Device

Technology Computer Aided Design Study of GaN MISFET With Double P-Buried Layers

A Novel GaN Metal-Insulator-Semiconductor High Electron Mobility Transistor Featuring Vertical Gate Structure

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