3D-stackable crossbar resistive memory based on Field Assisted Superlinear Threshold (FAST) selector

Jo, Sung‐Hyun; Kumar, T.; Narayanan, Sundar; Lü, Wei; Nazarian, Hagop

doi:10.1109/iedm.2014.7046999

Cited by 44 publications

(7 citation statements)

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“…The device can demonstrate bidirectional volatile switching with a large memory window, excellent turn-on current, and high turn on the slope. [131] Amorphous oxide is a major constituent of STL and can be deposited by either chemical or physical vapor deposition techniques. The threshold voltage of the selector can be tuned by controlling the thickness of the STL medium.…”

Section: Bipolar 1s1rmentioning

confidence: 99%

Recent Progress in Selector and Self‐Rectifying Devices for Resistive Random‐Access Memory Application

Dongale

Kamble

Kang

et al. 2021

Physica Rapid Research Ltrs

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The recent progress of selector and self-rectifying devices for resistive randomaccess memory applications is reviewed. In particular, the performance of crossbar arrays based on resistive switching (RS) devices, the sneak-path current issue, and possible solutions is discussed. The parameters and requirements of selector devices are elucidated here, and several types of selector devices, such as a transistor-assisted transistor-one resistor, unipolar one diode-one resistor, bipolar one selector-one resistor, and threshold switching selectors, are comprehensively discussed. In the case of self-rectifying devices, the recent progress in complementary RS devices, vacancy-modulated conductive oxide-based devices, and tunneling barrier-based RS devices is reviewed. The switching mechanisms and the geometrical configuration of the selector and self-rectifying RS devices are emphasized. Furthermore, comparative assessments of the different devices are evaluated. Finally, an overview of the gaps in previously reported devices is presented and some key improvements for future research direction suggested.

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Section: Bipolar 1s1rmentioning

confidence: 99%

Recent Progress in Selector and Self‐Rectifying Devices for Resistive Random‐Access Memory Application

Dongale

Kamble

Kang

et al. 2021

Physica Rapid Research Ltrs

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“…The Crossbar bitcell couples the resistive switching medium with a FAST selector device with a high RÂňon/Roff ratio and integrates with standard CMOS processes. The bitcell relies on the creation of microscopic conductive filaments in the switching medium through ion migration for the resistive element [3,4]. Figure 3(a) shows the cross section of the 1S1R (1 selector per 1 Resistive element) bitcell used.…”

Section: Reram Physical Characteristicsmentioning

confidence: 99%

Design for ReRAM-based main-memory architectures

Jagasivamani

Walden

Singh

et al. 2019

Proceedings of the International Symposium on Memory Systems

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With the anticipated scaling issues of DRAM memory technology and the increased need for higher density and bandwidth, several alternative memory technologies are being explored for the main memory system. One promising candidate is a variation of Resistive Random-Access Memory (ReRAM) which implements the memory bit-cells on Back-End-of-Line (BEOL) layers. This allows for fabrication of the processor logic and ReRAM main-memory to be implemented on the same chip. As the memory cells can be stacked vertically, the density of this memory also scales to 1-4F 2. This tight integration allows for a high amount of parallelism between the processor and memory systems and delivers low access granularity without sacrificing density or bandwidth. In this paper, we explore physical integration of a processor with a ReRAM-based main-memory system using the bitcell technology developed by Crossbar, Inc. We present Crossbar's ReRAM technology characteristics, the methodology and assumptions used for our digital implementation, and summarize the results obtained for different array configurations. Our results indicate that, in addition to the overhead for the ReRAM access circuits, the overall integrated area increases by 11% to 19%, based on the configuration at the 45nm process node. Results from architectural simulation comparing DRAM with ReRAM based architecture are presented.

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“…Most recent efforts focus on the implementation of 1S1R cells, with the novelty of introducing an extremely non-linear device inside the cell, acting as a selector [33], [34]. Equivalent to two in series diodes, these innovative cells are intended to provide a customizable voltage threshold starting from which the cell would be selected.…”

Section: A Spureus Writing In Non-selected Cells and Leakagementioning

confidence: 99%

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

García‐Redondo

Royer

López‐Vallejo

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-Resistive switching memories (RRAM) are an attractive alternative to non-volatile storage and non-conventional computing systems, but their behavior strongly depends on the cell features, driver circuit and working conditions. In particular, the circuit temperature and the writing voltage scheme become critical issues, determining resistive switching memories performance. These dependencies usually force a design time trade-off among reliability, device endurance and power consumption, and therefore imposing non-flexible functioning schemes and limiting the system performance. In this paper we present a writing architecture that ensures the correct operation no matter the working temperature, and allows the dynamic load of application oriented writing profiles. Thus, taking advantage of more efficient configurations, the system can be dynamically adapted to overcome RRAM intrinsic challenges. Several profiles are analyzed regarding power consumption, temperature-variations protection and operation speed, showing speed-ups near to 700 x compared against other published drivers.

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3D-stackable crossbar resistive memory based on Field Assisted Superlinear Threshold (FAST) selector

Cited by 44 publications

References 0 publications

Recent Progress in Selector and Self‐Rectifying Devices for Resistive Random‐Access Memory Application

Recent Progress in Selector and Self‐Rectifying Devices for Resistive Random‐Access Memory Application

Design for ReRAM-based main-memory architectures

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

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