3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance

Abstract

In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (Id-Vg) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed.

Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit

“…In this study, based on previous research, 29) we designed and fabricated a radiation-hardness MOSFET called a Z-gate layout MOSFET, 30) and conducted γ-rays irradiation experiments to clarify its tolerance to TID effects. In addition, a simulation model of the initial characteristics was constructed, and the characteristics could be represented by a standard MOSFET.…”

Editorial for the Special Issue on Miniaturized Transistors

“…Simulation studies such as this one are essential in optimizing devices without costly fabrication and laboratory measurements. Wang et al [10] proposed a novel Z-gate n-channel MOSFET layout to improve its radiation tolerance. The novel layout can be radiation-hardened with a fixed charge density at a shallow trench isolation of 3.5 ×3.33333pt1012 cm-2 while offering a small footprint and small gate capacitance when compared to the enclosed gate layout.…”