Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit

Abstract

A Z-gate layout MOSFET (ZLT) is expected to reduce the total ionizing dose (TID) effects which occur in the shallow trench isolation (STI) layer made of oxide. To verify the ZLT’s merit, the ZLT was designed and fabricated with the 0.18-µm standard CMOS technology. The ZLT was irradiated with Co60 γ-ray up to 10 Mrad, and its I-V characteristic fluctuation was compared with that of a standard straight gate layout MOSFET (SLT). As a result, it was confirmed that the Z-gate can suppress off-current fluctuations by 1/5, on-current fluctuations by 1/2 and threshold voltage fluctuations by 1/6 compared with the SLT. Since the size penalty of the ZLT is small, it is possible to improve the radiation hardness of CMOS LSIs circuit by just replacing SLTs to ZLTs.