3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks

Park, Yu Jeong; Kwon, Hui Tae; Kim, Boram; Lee, Won Joo; Wee, Dae Hoon; Choi, Hyun‐Seok; Park, Byung‐Gook; Lee, Jong-Ho; Kim, Yoon

doi:10.1109/ted.2018.2881972

Cited by 41 publications

(30 citation statements)

References 25 publications

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“…In the case of the ImageNet classification challenge, state-of-the-art deep neural network (DNN) architectures have 5~155M synaptic weight parameters [16]. In order to implement efficiently a large-size artificial neural network on a limited-size hardware chip, we proposed the 3-D stacked synapse array structure ( Figure 1) in the previous work [11]. Unit synapse cell is composed of two CTF devices having two drain nodes (D(+), D(−)) and common source node(S).…”

Section: Design Methods Of 3-d Synapse Array Architecturementioning

confidence: 99%

“…The requirements of a synapse device to implement a neuromorphic system are as follows: small cell size, low-energy consumption, multi-level operations, symmetric and linear weight change, high endurance and complementary metal-oxide semiconductor (CMOS) compatibility [5]. Various memory devices, such as static random-access memories (SRAM) [7], resistive random-access memories (RRAM) [8], phase change memories (PCM) [9], floating gate-memories (FG-memory) [10] and charge-trap flash memories [11] have been proposed to implement the synapse operation. Among them, charge-trap flash (CTF) devices have good CMOS compatibility and excellent reliability [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

“…In our previous work, we proposed a 3-D stacked synapse array based on a charge trap flash (CTF) device [11]. Three-dimensional stacking technology is currently used in the commercialized Not AND (NAND) flash memory products for ultra-high density [14].…”

Section: Introductionmentioning

confidence: 99%

“…The rest of the paper is structured as follows: Section 2 contains design methods based on the viewpoint of a full-chip architecture. In this section, we review the 3-D stacked synapse array structure developed in the previous work [11] and propose an improved version of the 3-D stacked synapse array architecture to solve the unwanted problem of the previous version. In Section 3, we propose an improved programming method to obtain linear and symmetric conductance changes.…”

Section: Introductionmentioning

confidence: 99%

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3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application

Choi

Park²,

Lee

et al. 2019

Electronics

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In order to address a fundamental bottleneck of conventional digital computers, there is recently a tremendous upsurge of investigations on hardware-based neuromorphic systems. To emulate the functionalities of artificial neural networks, various synaptic devices and their 2-D cross-point array structures have been proposed. In our previous work, we proposed the 3-D synapse array architecture based on a charge-trap flash (CTF) memory. It has the advantages of high-density integration of 3-D stacking technology and excellent reliability characteristics of mature CTF device technology. This paper examines some issues of the 3-D synapse array architecture. Also, we propose an improved structure and programming method compared to the previous work. The synaptic characteristics of the proposed method are closely examined and validated through a technology computer-aided design (TCAD) device simulation and a system-level simulation for the pattern recognition task. The proposed technology will be the promising solution for high-performance and high-reliability of neuromorphic hardware systems.

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Section: Design Methods Of 3-d Synapse Array Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application

Choi

Park²,

Lee

et al. 2019

Electronics

Self Cite

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“…Recently, a bio-inspired neuromorphic system based on a spiking neural network (SNN) has been widely investigated because of its power-efficiency and parallel signal processing properties [2][3][4][5]. With regard to its application, the neuromorphic system, which is a hardware implementation of an artificial neural network, has been utilized mostly for pattern recognition [6][7][8][9][10], but also as a denoising auto encoder [11], for color image reconstruction [12], and for speech recognition [13]. In addition, various kinds of electronic devices have been studied as an artificial synaptic device, a crucial building block for constructing neuromorphic systems, including resistive switching materials [14][15][16][17], phase change materials [18][19][20], ferroelectric materials [21,22], and transistors [23][24][25].…”

Section: Introductionmentioning

confidence: 99%

Solving Overlapping Pattern Issues in On-Chip Learning of Bio-Inspired Neuromorphic System with Synaptic Transistors

Kim

Park

2019

Electronics

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Recently, bio-inspired neuromorphic systems have been attracting widespread interest thanks to their energy-efficiency compared to conventional von Neumann architecture computing systems. Previously, we reported a silicon synaptic transistor with an asymmetric dual-gate structure for the direct connection between synaptic devices and neuron circuits. In this study, we study a hardware-based spiking neural network for pattern recognition using a binary modified National Institute of Standards and Technology (MNIST) dataset with a device model. A total of three systems were compared with regard to learning methods, and it was confirmed that the feature extraction of each pattern is the most crucial factor to avoiding overlapping pattern issues and obtaining a high pattern classification ability.

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All‐Solid‐State Ion Synaptic Transistor for Wafer‐Scale Integration with Electrolyte of a Nanoscale Thickness

Lee

Kim

et al. 2021

Adv Funct Materials

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Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation, and low power consumption. To implement neuromorphic hardware based on deep neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For ideal hardware DNN, not only scalability and low power consumption, but also a linear and symmetric conductance change with the large number of conductance levels are required. Here an all-solid-state polymer electrolyte-gated synaptic transistor (pEGST) was fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition (iCVD) process. The pEGST showed good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ/pulse. Selected 128 levels from 8,192 used to identify handwritten digits in the MNIST database with the aid of a multilayer perceptron, resulting in a recognition rate of 91.7 %.

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3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks

Cited by 41 publications

References 25 publications

3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application

3-D Synapse Array Architecture Based on Charge-Trap Flash Memory for Neuromorphic Application

Solving Overlapping Pattern Issues in On-Chip Learning of Bio-Inspired Neuromorphic System with Synaptic Transistors

All‐Solid‐State Ion Synaptic Transistor for Wafer‐Scale Integration with Electrolyte of a Nanoscale Thickness

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