All‐Solid‐State Ion Synaptic Transistor for Wafer‐Scale Integration with Electrolyte of a Nanoscale Thickness

Abstract

Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation, and low power consumption. To implement neuromorphic hardware based on deep neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For ideal hardware DNN, not only scalability and low power consumption, but also a linear and symmetric conductance change with the large number of conductance levels are required. Here an all-solid-state polymer electrolyte-gated synaptic transistor (pEGST) was fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition (iCVD) process. The pEGST showed good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ/pulse. Selected 128 levels from 8,192 used to identify handwritten digits in the MNIST database with the aid of a multilayer perceptron, resulting in a recognition rate of 91.7 %.

Mnemonic-Opto-Synaptic Transistor for In-Sensor Vision System

“…These parameters are used for the subsequent software simulations. It is well known that a large number of states is preferred to enhance the performance of pattern recognition in a synaptic device [20][21][22]. In this context, it was also con rmed that the P-D characteristics for N pulse of 64 and 128 were achievable by delicately tuning the gate pulse, as shown in Figure S3.…”

“…It is attributed to electron trapping in the CTL by applied positive depression gate voltage (V G,dep ); i.e., it suppresses inversion at the channel surface. This is analogous to the depression operation to reduce the synaptic weight in an arti cial synapse [20][21][22]. The magnitude of V G,dep is 9 V and its pulse width is 10 μs.…”

Implementation of Synaptic Device Using Ultraviolet Ozone Treated Water‐in‐Bisalt/Polymer Electrolyte‐Gated Transistor

“…In an ideal synaptic device, both NL and AR factors are zero. [ 48–51 ] As identified in Figure 6a, the NL values of the UVO‐treated WEST (w/UVO) are 0.32 in LTP and −0.55 in LTD, respectively, which are very close to zero compared to those of the untreated WEST 5.91 in LTP and −6.11 in LTD, respectively. In addition, the calculated AR of the UVO‐treated WEST is 0.089, which is 1/10 of that of untreated WEST (0.83).…”

Multi-functional multi-gate one-transistor process-in-memory electronics with foundry processing and footprint reduction

“…In our previous published work on the standard bottom-gate transistors for the artificial synaptic devices, we have proposed that the terminal voltages such as gate voltages and drain voltages could qualitatively adjust the artificial synaptic behaviors for a standard transistor 41 . This multi-terminal-designinduced V CG effect, in addition to the effect of the typical gate (bottom gate, top gate, or side gate) voltages, could impact the artificial synaptic behaviors 31,42 . The multi-terminal structure improves the controllability of the device when compared to the previous structures with only typical gates (bottom gate, top gate, or side gate).…”

“…As shown in Fig. 5g, additional synaptic weight modulation such as potentiation could be achieved by the combinations of the top gate and control gate voltage 42,43 . The base for the drain current increases after the pulse stimulations, which suggests a potentiation.…”