28nm FDSOI technology platform for high-speed low-voltage digital applications

Planes, N.; Weber, O.; Barral, V.; Haendler, S.; Noblet, D.; Croain, Damien; Bocat, M.; Sassoulas, Pierre-Olivier; Federspiel, X.; Cros, A.; Bajolet, A.; Richard, E.; Dumont, B.; Perreau, P.; Petit, D.; Golanski, Dominique; Fenouillet-Béranger, C.; Guillot, Nicolas; Rafik, M.; Huard, V.; Puget, S.; Montagner, X.; Jaud, M.-A.; Rozeau, O.; Saxod, O.; Wacquant, F.; Monsieur, F.; Barge, D.; Pinzelli, L.; Mellier, M.; Bœuf, F.; Arnaud, F.; Haond, M.

doi:10.1109/vlsit.2012.6242497

Cited by 332 publications

(148 citation statements)

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“…One of the most promising lines is the development of energy-efficient processing architectures building blocks that would significantly enhance the energyproportionality of server processing power at the deep submicron era (i.e., beyond 28 nm technology nodes). The development of these building blocks will be achieved by using emerging technologies such as fully depleted silicon on insulator (FDSOI) [25] and gate-allaround nanowires [26], and integrated microfluidic cooling and power delivery [27]. This development would require modelling the power and thermal dissipations involved in the processing units, memory hierarchy, and the cooling and power delivery networks at the server level.…”

Section: Circuit Microarchitecturementioning

confidence: 99%

Energy Challenges for ICT

Fagas¹,

Gallagher²,

Gammaitoni³

et al. 2017

ICT - Energy Concepts for Energy Efficiency and Sustainability

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The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute significantly to the reduction of CO 2 emission and enhance resource efficiency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manufacturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource efficiency, a multidisciplinary ICT-energy community needs to be brought together covering devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded systems, efficient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging field and a common framework to strive towards energy-sustainable ICT.

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Section: Circuit Microarchitecturementioning

confidence: 99%

Energy Challenges for ICT

Fagas¹,

Gallagher²,

Gammaitoni³

et al. 2017

ICT - Energy Concepts for Energy Efficiency and Sustainability

View full text Add to dashboard Cite

show abstract

“…Tolerance to low channel doping additionally boosts mobility and performance and reduces local (statistical) variability [11]- [16]. This research and corresponding technology development has culminated in the introduction of 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS by STMicroelectronics [17] and 22-and 14-nm FinFET CMOS by Intel [18] and Samsung [19]. It has been speculated that the scalability of FDSOI can extend planar CMOS technology down to 10 nm [20], and FinFETs can extend CMOS technology down to 7 nm [21].…”

mentioning

confidence: 99%

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

Wang

Al-Ameri

Wang

et al. 2015

IEEE Trans. Electron Devices

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Abstract-In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

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“…This will result in overall reduction of the total variability in both the nMOSFET and pMOSFET by approximately 7-8mV. In contrast, FinFETs and FD SOI transistorts tolerate low channel doping, practically eliminating the RDD effects, and dramatically reducing the statistical variability [16] [17]. [28], the σV T scattering cannot completely describe the I ON variation behavior.…”

Section: Simulation Methodologymentioning

confidence: 99%

“…As a result in its 22nm technology generation Intel introduced the novel 'tri-gate' FinFET architecture [15] that has superior electrostatic integrity, tolerates low channel doping and has the potential to reduce significantly the statistical variability [16]. Fully-depleted (FD) planar SOI transistors are also introduced by ST at 28nm CMOS [17] to reduce the statistical variability. Many technology providers, however, continue to rely on conventional bulk transistors at the 20 nm CMOS technology generation planed for early introduction in 2013 [18].…”

Section: Introductionmentioning

confidence: 99%

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Wang

Adamu-Lema

Cheng

et al. 2013

IEEE Trans. Electron Devices

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Abstract-Conventional bulk CMOS, which is arguably most vulnerable to statistical variability, has been the workhorse of the electronic industry for more than three decades. In this paper, the dependence of the statistical variability of key figures of merit on gate geometry, temperature and body bias in 25nm gate-length MOSFETs, representative for the 20nm CMOS technology generation, are systematically investigated using 3D statistical simulations. The impact of all relevant sources of statistical variability is taken into account. The geometry dependence of the threshold voltage dispersion (and indeed the dispersion of other key transistor figures of merit) does not necessarily follow the Pelgrom's law due to the complex non-uniform channel doping and the interplay of different statistical-variability sources. The DIBL variation for example follows a log-normal distribution. The temperature significantly affects the magnitudes of threshold-voltage, sub-threshold slope, on/off currents and the corresponding statistical distributions. Reverse body bias increases the threshold voltage and its fluctuation while forward body bias reduces both of them.

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28nm FDSOI technology platform for high-speed low-voltage digital applications

Cited by 332 publications

References 0 publications

Energy Challenges for ICT

Energy Challenges for ICT

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

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