1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in $0.13~\mu \text{m}$ CMOS

Bayram, Erkan; Aref, Ahmed Farouk; Saeed, Mohamed; Negra, Renato

doi:10.1109/tcsi.2017.2715899

Cited by 26 publications

(7 citation statements)

References 23 publications

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“…Figure shows the architecture of the dual‐loop DLLs. Based on this architecture, various works are reported …”

Section: Conventional Architecturesmentioning

confidence: 99%

“…Various DLLs have been reported with novel delay elements 4,[11][12][13][14] to achieve the above-mentioned features. These DLLs are majorly categorized as analog 4,[12][13][14] and digital [15][16][17][18] based on the control mechanism of the delay element or the delay line involved.…”

Section: Figure 1 Basic Architecture Of Dll For Multiphase Clock Genementioning

confidence: 99%

“…However, skew error and jitter are increased due to continuous change of phase selection among quantized delay lines with supply and temperature variations. 14 To overcome these problems, dual loop architectures 11,19 have been proposed, where fine-tune delay line is added to a digital DLL to obtain the continuous phase. However, these proposals make the circuitry more complex and increase power consumption and area In deep submicron CMOS process, it is well-known that time-domain resolution of a digital signal edge transition is superior to voltage resolution of analog signals.…”

Section: Figure 1 Basic Architecture Of Dll For Multiphase Clock Genementioning

confidence: 99%

“…Based on this architecture, various works are reported. 11,19 FIGURE 4 Conventional digital DLL architecture…”

Section: Dual Loop Dllsmentioning

confidence: 99%

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Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS

Kammari

Pasupureddi

2019

Circuit Theory & Apps

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Summary In this work, a robust, low‐power, widely linear multiphase clock generation and multiplying delay‐locked loop (MPCG‐MDLL) architecture is realized, using a new differential charge‐mode delay element circuit topology. The heart of any MPCG‐MDLL architecture is the delay element, and hence, the characteristics of the delay element influence the overall performance of the MPCG‐MDLL, in terms of its specifications such as peak‐to‐peak jitter, lock range, delay range, control voltage range, and power consumption. The proposed eight‐phase MPCG‐MDLL along with the charge‐mode delay element outperforms the conventional MPCG‐MDLLs that deploy delay elements such as a current‐starved inverter (CSI), wide‐range CSI, triply controlled delay cell, digital‐controlled delay element, and the like. The eight‐phase MPCG‐MDLL along with the new charge‐mode delay element circuit topology is implemented in 1.2‐V, 65‐nm CMOS technology. The performance results show that the eight‐stage delay line has a delay range from 640 to 960 ps over the rail‐to‐rail control voltage range. The implemented MPCG‐DLL is robust over process, voltage, and temperature (PVT) corners and exhibits a lock range of 400 MHz and a peak‐to‐peak jitter of less than 60 fs for all the DLL output phases and peak‐to‐peak jitter of 0.54 and 1.24 ps for the synthesized 5‐GHz clocks for an input reference clock frequency of 1.25 GHz. The MPCG‐MDLL consumes 4.74 mW of power and occupies an area of 0.017 mm2.

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“…Figure shows the architecture of the dual‐loop DLLs. Based on this architecture, various works are reported …”

Section: Conventional Architecturesmentioning

confidence: 99%

Section: Figure 1 Basic Architecture Of Dll For Multiphase Clock Genementioning

confidence: 99%

Section: Figure 1 Basic Architecture Of Dll For Multiphase Clock Genementioning

confidence: 99%

“…Based on this architecture, various works are reported. 11,19 FIGURE 4 Conventional digital DLL architecture…”

Section: Dual Loop Dllsmentioning

confidence: 99%

See 2 more Smart Citations

Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS

Kammari

Pasupureddi

2019

Circuit Theory & Apps

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“…But DSLC reduces the bandwidth of DLL in lock state and the efficiency of the DSLC depends on clock quality and PVT variations in the TSDPD. In [17] a dead-zone free PD with XOR-based controlled counter is used to reduce the jitter issue. PD is designed to detect 1ps delay difference and it only activates for fine delay line locking as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

et al. 2020

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This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on 0.18 µm CMOS technology with an operational range of 350∼900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 mm 2. INDEX TERMS All digital delay locked loop (ADDLL), digital controller, jitter, light detection and ranging (LIDAR), time to digital converter (TDC).

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A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

Kammari

Pasupureddi

2019

Communications in Computer and Information Science

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1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in $0.13~\mu \text{m}$ CMOS

Cited by 26 publications

References 23 publications

Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS

Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS

A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor

A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

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