A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

Kammari, Raviteja; Pasupureddi, Vijaya Sankara Rao

doi:10.1007/978-981-32-9767-8_18

Communications in Computer and Information Science

2019

DOI: 10.1007/978-981-32-9767-8_18

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A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

Raviteja Kammari

Vijaya Sankara Rao Pasupureddi

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2022

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Cited by 1 publication

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A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

Cited by 1 publication

References 8 publications

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