The maximum oscillation frequency (fmax) quantifies the practical upper bound for useful circuit operation. We report here an fmax of 70 GHz in transistors using epitaxial graphene grown on the C-face of SiC. This is a significant improvement over Si-face epitaxial graphene used in the prior high-frequency transistor studies, exemplifying the superior electronics potential of C-face epitaxial graphene. Careful transistor design using a high κ dielectric T-gate and self-aligned contacts further contributed to the record-breaking fmax.

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The development of graphene electronics [1,2] requires the integration of graphene devices withSi-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer [3][4][5] and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene [6,7] . Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating)surface, and graphene nanostructures with exceptional properties [8][9][10][11] have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning [9,12,13] .However, the temperatures required in this structured growth process are too high for silicontechnology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) [14][15][16] a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices [17,18] preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing.

Structured growth of high quality graphene is necessary for technological development of carbon based electronics. Specifically, control of the bunching and placement of surface steps under epitaxial graphene on SiC is an important consideration for graphene device production. We demonstrate lithographically patterned evaporated amorphous carbon corrals as a method to pin SiC surface steps. Evaporated amorphous carbon is an ideal step-flow barrier on SiC due to its chemical compatibility with graphene growth and its structural stability at high temperatures, as well as its patternability. The amorphous carbon is deposited in vacuum on SiC prior to graphene growth. In the graphene furnace at temperatures above 1200 • C, mobile SiC steps accumulate at these amorphous carbon barriers, forming an aligned step free region for graphene growth at temperatures above 1330 • C. AFM imaging and Raman spectroscopy support the formation of quality step-free graphene sheets grown on SiC with the step morphology aligned to the carbon grid.

A purely planar graphene/SiC field effect transistor is presented here. The horizontal current flow over one-dimensional tunneling barrier between planar graphene contact and coplanar two-dimensional SiC channel exhibits superior on/off ratio compared to conventional transistors employing vertical electron transport. Multilayer epitaxial graphene (MEG) grown on SiC(0001̅) was adopted as the transistor source and drain. The channel is formed by the accumulation layer at the interface of semi-insulating SiC and a surface silicate that forms after high vacuum high temperature annealing. Electronic bands between the graphene edge and SiC accumulation layer form a thin Schottky barrier, which is dominated by tunneling at low temperatures. A thermionic emission prevails over tunneling at high temperatures. We show that neglecting tunneling effectively causes the temperature dependence of the Schottky barrier height. The channel can support current densities up to 35 A/m.

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