We present a robust method for forming high quality ohmic contacts to graphene, which improves the contact resistance by nearly 6000 times compared to untreated metal/graphene interfaces. The optimal specific contact resistance for treated Ti/Au contacts is found to average <10−7 Ω cm2. Additionally, we examine Al/Au, Ti/Au, Ni/Au, Cu/Au, Pt/Au, and Pd/Au contact metallizations and find that most metallizations result in similar specific contact resistances in this work regardless of the work function difference between graphene and the metal overlayer. The results presented in this work serve as a foundation for achieving ultralow resistance ohmic contacts to graphene for high speed electronic and optoelectronic applications.

A promising route for the synthesis of large-area graphene, suitable for standard device fabrication techniques, is the sublimation of silicon from silicon carbide at elevated temperatures (>1200 degrees C). Previous reports suggest that graphene nucleates along the (110n) plane, known as terrace step edges, on the silicon carbide surface. However, to date, a fundamental understanding of the nucleation of graphene on silicon carbide is lacking. We provide the first direct evidence that nucleation of epitaxial graphene on silicon carbide occurs along the (110n) plane and show that the nucleated graphene quality improves as the synthesis temperature is increased. Additionally, we find that graphene on the (110n) plane can be significantly thicker than its (0001) counterpart and appears not to have a thickness limit. Finally, we find that graphene along the (110n) plane can contain a high density of structural defects, often the result of the underlying substrate, which will undoubtedly degrade the electronic properties of the material. Addressing the presence of non-uniform graphene that may contain structural defects at terrace step edges will be key to the development of a large-scale graphene technology derived from silicon carbide.

We present the integration of epitaxial graphene with thin film dielectric materials for the purpose of graphene transistor development. The impact on epitaxial graphene structural and electronic properties following deposition of Al(2)O(3), HfO(2), TiO(2), and Ta(2)O(5) varies based on the choice of dielectric and deposition parameters. Each dielectric film requires the use of a nucleation layer to ensure uniform, continuous coverage on the graphene surface. Graphene quality degrades most severely following deposition of Ta(2)O(5), while the deposition if TiO(2) appears to improve the graphene carrier mobility. Finally, we discuss the potential of dielectric stack engineering for improved transistor performance.

We explore the effect of high-κ dielectric seed layer and overlayer on carrier transport in epitaxial graphene. We introduce a novel seeding technique for depositing dielectrics by atomic layer deposition that utilizes direct deposition of high-κ seed layers and can lead to an increase in Hall mobility up to 70% from as-grown. Additionally, high-κ seeded dielectrics are shown to produce superior transistor performance relative to low-κ seeded dielectrics and the presence of heterogeneous seed/overlayer structures is found to be detrimental to transistor performance, reducing effective mobility by 30-40%. The direct deposition of high-purity oxide seed represents the first robust method for the deposition of uniform atomic layer deposited dielectrics on epitaxial graphene that improves carrier transport.