We present a robust method for forming high quality ohmic contacts to graphene, which improves the contact resistance by nearly 6000 times compared to untreated metal/graphene interfaces. The optimal specific contact resistance for treated Ti/Au contacts is found to average <10−7 Ω cm2. Additionally, we examine Al/Au, Ti/Au, Ni/Au, Cu/Au, Pt/Au, and Pd/Au contact metallizations and find that most metallizations result in similar specific contact resistances in this work regardless of the work function difference between graphene and the metal overlayer. The results presented in this work serve as a foundation for achieving ultralow resistance ohmic contacts to graphene for high speed electronic and optoelectronic applications.

We present a novel method for the direct metal-free growth of graphene on sapphire that yields high quality films comparable to that of graphene grown on SiC by sublimation. Graphene is synthesized on sapphire via the simple decomposition of methane at 1425-1600 °C. Film quality was found to be a strong function of growth temperature. The thickness, structure, interface characteristics, and electrical transport properties were characterized in order to understand the utility of this material for electronic devices. Graphene synthesized on sapphire is found to be strain relieved, with no evidence of an interfacial buffer layer. There is a strong correlation between the graphene structural quality and carrier mobility. Room temperature Hall effect mobility values were as high as 3000 cm(2)/(V s), while measurements at 2 K reached values of 10,500 cm(2)/(V s). These films also display evidence of the quantum Hall effect. Field effect transistors fabricated from this material had a typical current density of 200 mA/mm and transconductance of 40 mS/mm indicating that material performance may be comparable to graphene on SiC.

We directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. Upon successful buffer elimination, carrier mobility increases from an average of 800 cm(2)/(V s) to >2000 cm(2)/(V s). Additionally, graphene transistor current saturation increases from 750 to >1300 mA/mm, and transconductance improves from 175 mS/mm to >400 mS. Finally, we report a 10× improvement in the extrinsic current gain response of graphene transistors with optimal extrinsic current-gain cutoff frequencies of 24 GHz.

A promising route for the synthesis of large-area graphene, suitable for standard device fabrication techniques, is the sublimation of silicon from silicon carbide at elevated temperatures (>1200 degrees C). Previous reports suggest that graphene nucleates along the (110n) plane, known as terrace step edges, on the silicon carbide surface. However, to date, a fundamental understanding of the nucleation of graphene on silicon carbide is lacking. We provide the first direct evidence that nucleation of epitaxial graphene on silicon carbide occurs along the (110n) plane and show that the nucleated graphene quality improves as the synthesis temperature is increased. Additionally, we find that graphene on the (110n) plane can be significantly thicker than its (0001) counterpart and appears not to have a thickness limit. Finally, we find that graphene along the (110n) plane can contain a high density of structural defects, often the result of the underlying substrate, which will undoubtedly degrade the electronic properties of the material. Addressing the presence of non-uniform graphene that may contain structural defects at terrace step edges will be key to the development of a large-scale graphene technology derived from silicon carbide.