We report a direct correlation between carrier mobility and Raman topography of epitaxial graphene (EG) grown on silicon carbide (SiC). We show the Hall mobility of material on the Si-face of SiC [SiC(0001)] is not only highly dependent on thickness uniformity but also on monolayer s st tr ra ai in n uniformity. Only when both thickness and strain are uniform over a significant fraction (> 40%) of the device active area does the mobility exceed 1000 cm 2 /V-s. Additionally, we achieve high mobility epitaxial graphene (18,100 cm 2 /V-s at room temperature) on the C-face of SiC [SiC(000-1)] and show that carrier mobility depends strongly on the graphene layer stacking. These findings provide a means to rapidly estimate carrier mobility and provide a guide to achieve very high mobility in epitaxial graphene. Our results suggest that ultra-high mobilities (>50,000 cm 2 /V-s) are achievable via the controlled formation of uniform, rotationally faulted epitaxial graphene.The recent success of graphene transistor operation in the giga-hertz range has solidified the potential of this material for high speed electronic applications. 1,2 Realization of graphene technologies at commercial scales, however, necessitates large-area graphene production, as well as the ability to rapidly characterize its structural and electronic quality. Graphene films can be produced by mechanical exfoliation from bulk graphite, 3,4 reduction of graphite-oxide, 5,6 chemical vapor deposition on catalytic films, 7 or via Si-sublimation from bulk SiC substrates. 8 9, -10,11, 12 The last technique currently appears to hold the most promise for large-area electronic grade graphene, and already shows tremendous potential for high-frequency device technologies. 2 Nevertheless, precise control of the graphene electronic properties (i.e. mobility) over large areas is necessary to enable graphene-based technological applications. Realization of such control will come through an intimate understanding of the process-propertyperformance relationship and the role that graphene thickness, strain, and layer stacking plays in this relationship over very large areas up to full wafers. Of the characterization techniques used for layer thickness determination, 13 ,14,15, -16,17,18, 19 Raman spectroscopy is arguably the simplest and fastest, especially for exploring monolayer EG on SiC(0001) (referred to as EG Si )and EG layer stacking on SiC(000-1) (referred to as EG c ). [15][16][17][18][19] Characterization of EG via Raman spectroscopy requires fitting the 2D Raman peak. 15,16,20 Raman spectra of EG Si fit by one or four Lorentzian functions are characteristic of monolayer or bilayer graphene, respectively. 15 Figure 1a demonstrates layer thickness evaluation for monolayer and bilayer EG Si via Lorentzian fitting of the 2D Raman spectra. To further validate these thickness measurements, cross-sectional transmission electron microscopy (TEM) was performed (Fig. 1b,c). The TEM micrographs in Fig.1b,c include a transition layer (Layer 0), which is in dire...

A promising route for the synthesis of large-area graphene, suitable for standard device fabrication techniques, is the sublimation of silicon from silicon carbide at elevated temperatures (>1200 degrees C). Previous reports suggest that graphene nucleates along the (110n) plane, known as terrace step edges, on the silicon carbide surface. However, to date, a fundamental understanding of the nucleation of graphene on silicon carbide is lacking. We provide the first direct evidence that nucleation of epitaxial graphene on silicon carbide occurs along the (110n) plane and show that the nucleated graphene quality improves as the synthesis temperature is increased. Additionally, we find that graphene on the (110n) plane can be significantly thicker than its (0001) counterpart and appears not to have a thickness limit. Finally, we find that graphene along the (110n) plane can contain a high density of structural defects, often the result of the underlying substrate, which will undoubtedly degrade the electronic properties of the material. Addressing the presence of non-uniform graphene that may contain structural defects at terrace step edges will be key to the development of a large-scale graphene technology derived from silicon carbide.

We present the integration of epitaxial graphene with thin film dielectric materials for the purpose of graphene transistor development. The impact on epitaxial graphene structural and electronic properties following deposition of Al(2)O(3), HfO(2), TiO(2), and Ta(2)O(5) varies based on the choice of dielectric and deposition parameters. Each dielectric film requires the use of a nucleation layer to ensure uniform, continuous coverage on the graphene surface. Graphene quality degrades most severely following deposition of Ta(2)O(5), while the deposition if TiO(2) appears to improve the graphene carrier mobility. Finally, we discuss the potential of dielectric stack engineering for improved transistor performance.

In this letter, we present state-of-the-art performance of top-gated graphene n-FETs and p-FETs fabricated with epitaxial graphene layers grown on Si-face 6H-SiC substrates on 50-mm wafers. The current-voltage characteristics of these devices show excellent saturation with ON-state current densities (I on) of 0.59 A/mm at V ds = 1 V and 1.65 A/mm at V ds = 3 V. I on /I off ratios of 12 and 19 were measured at V ds = 1 and 0.5 V, respectively. A peak extrinsic g m as high as 600 mS/mm was measured at V ds = 3.05 V, with a gate length of 2.94 μm. The field-effect mobility versus effective electric field (E eff) was measured for the first time in epitaxial graphene FETs, where record field-effect mobilities of 6000 cm 2 /V • s for electrons and 3200 cm 2 /V • s for holes were obtained at E eff ∼ 0.27 MV/cm.

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The synthesis of epitaxially oriented Si nanowires at high growth rates (>1 microm/min) was demonstrated on (111) Si substrates using Al as the catalyst. The use of high H(2) and SiH(4) partial pressures was found to be effective at reducing problems associated with Al oxidation and nanowire nucleation, enabling growth of high aspect ratio structures at temperatures ranging from 500 to 600 degrees C with minimal tapering of the diameter. Because of the high growth rate observed, the Al catalyst is believed to be in the liquid state during the growth. Four-point resistance measurements and back-gated current-voltage measurements indicate that the wires are p-type with an average resistivity of 0.01 +/- 0.004 Omega-cm. These results suggest that Al is incorporated into the Si nanowires under these conditions at concentrations higher than the solubility limit (5-6 x 10(18) cm(-3)) for Al in Si at 550 degrees C. This work demonstrates that Al can serve as both an effective catalyst and p-type dopant for the growth of Si nanowires.

A systematic study of tin-catalyzed vapor−liquid−solid (VLS) growth of silicon nanowires by plasma-enhanced chemical vapor deposition at temperatures ranging from 300 to 400 °C is presented. Wire structure, morphology, and growth rate are characterized as a function of process variables. The nanowires are observed to have a crystalline core with a polycrystalline shell due to simultaneous VLS axial growth and vapor−solid radial growth. Axial and radial growth rates are controllable through hydrogen dilution of the plasma which affects the concentration of silane radicals in the plasma. In addition, wire length is observed to saturate with increasing growth time. Post growth chemical analysis suggests this is due to etching and disappearance of tin seeds in the hydrogen plasma which occur in parallel with wire growth. This opens up the possibility of a unique in situ approach to fabricating metal-free nanowire arrays for device applications.

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