This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.
The design of digital-analog mixed SoC involves RF/analog and digital domains, how to effectively improve the design reliability and to reduce the development cycles has become a research hotspot. This paper establishes the appropriate behavioral models of RF / analog / digital IP modules, and carries out the behavioral simulation based on the built mixed-domain simulation platform and the behavioral libraries of RF/analog/digital IP module, which enhances the reliability and stability of mixed SoC design, and reduces the design cycle. Those explorations may be helpful to the designers of digital-analog mixed SoC.
The classical model in digital DC-DC converter is digital pulse width mode (DPWM), but the digital pulse frequency mode (DPFM) is very important in DC-DC converter with light load. This paper presents the different application environments and the effect between the two modes. There are two common different DPFM structures analyzed in this paper. And a novel DPFM circuit is proposed, which needs only external clock, not affected by the duty cycle of the clock. The circuit and layout are designed with 0.13um CMOS technology. The simulation results of the circuit meet the requirements of design.
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