This paper presents a novel scheme for IF digital software radio receiver application, which integrates a high performance AID converter and high-speed digital down converter (DDC) block into a SoC (system on chip) based on 32-bit RISC CPU. The proposed design can transform intermediate frequenc y (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing. The simulation results indicate that The SFDR of ADC can achieve 88dB, and the SFDR of the DDC can reach to 70.59dBFS. The s y nthesized results of digital parts for the proposed SoC architecture on 0.18um CMOS technolog y reveals a maximum clock frequenc y of 116MHz and a total area of digital parts is 5.662mm 2 , and the corresponding power consumption is below 150 mW • The ADC can reach to 250MSPS, whose power consumption is 263.6mW. The test results illuminates that the chip can work well. This design will have a good potential for wireless communication applications.