This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.
The design of digital-analog mixed SoC involves RF/analog and digital domains, how to effectively improve the design reliability and to reduce the development cycles has become a research hotspot. This paper establishes the appropriate behavioral models of RF / analog / digital IP modules, and carries out the behavioral simulation based on the built mixed-domain simulation platform and the behavioral libraries of RF/analog/digital IP module, which enhances the reliability and stability of mixed SoC design, and reduces the design cycle. Those explorations may be helpful to the designers of digital-analog mixed SoC.
This paper will discuss how we integrated Verification Planner in our verification environment to generate better reports that can be used to track the progress of verification with the project manager. Using Verification Planner we were able to add coverage information to the Verification IP’s Excel based verification plans. We can then take advantage of Excel to generate better reports. Using a top-level plan, we were able to generate a summary page that could be shared with project manager, giving them the information they needed.
This paper describes the use of VMM, Verification IP, and several of the new VMM Applications to quickly develop a verification environment for an AHB-Based system. VIP such as Synopsys DesignWare AHB Master and Monitor transactors enabled generation of valid transaction and ensured AHB protocol compliance. VMM sub-environment were used to encapsulate these components and simplify their reuse in higher level test environment.
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