A 16-bit multi-channel simultaneous sampling ADC of wide analog input was designed. This ADC had a maximum conversion rate of 250[kSPS]. The ADC was implemented in 0.6[um] 2P3M standard CMOS process+high voltage CMOS process. For ±10 [V]/10[kHz] sine analog input and 250[kSPS] sampling rate, the testing result of the ADC at room temperature is that INL is 1.7[LSB], SINAD is 85.3[dB], EFS-is 0.055[%FS], EFS+ is 0.039[%FS].
The classical model in digital DC-DC converter is digital pulse width mode (DPWM), but the digital pulse frequency mode (DPFM) is very important in DC-DC converter with light load. This paper presents the different application environments and the effect between the two modes. There are two common different DPFM structures analyzed in this paper. And a novel DPFM circuit is proposed, which needs only external clock, not affected by the duty cycle of the clock. The circuit and layout are designed with 0.13um CMOS technology. The simulation results of the circuit meet the requirements of design.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.