2013
DOI: 10.4028/www.scientific.net/amm.446-447.901
|View full text |Cite
|
Sign up to set email alerts
|

A Multi-Channel, 16-Bit, 250[kHz], Simultaneous Sampling ADC

Abstract: A 16-bit multi-channel simultaneous sampling ADC of wide analog input was designed. This ADC had a maximum conversion rate of 250[kSPS]. The ADC was implemented in 0.6[um] 2P3M standard CMOS process+high voltage CMOS process. For ±10 [V]/10[kHz] sine analog input and 250[kSPS] sampling rate, the testing result of the ADC at room temperature is that INL is 1.7[LSB], SINAD is 85.3[dB], EFS-is 0.055[%FS], EFS+ is 0.039[%FS].

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2017
2017
2023
2023

Publication Types

Select...
1
1

Relationship

0
2

Authors

Journals

citations
Cited by 2 publications
(1 citation statement)
references
References 4 publications
0
1
0
Order By: Relevance
“…The LTC2325 supports SPI serial interfaces in both CMOS mode and LVDS mode. CMOS mode uses single terminal output for each channel and LVDS mode uses differential output for each channel [8][9]. In SDR mode, data is transmitted at the rising edge of the signal, while in DDR mode, data can be transmitted at both the rising and falling edge of the signal, so the data transmission rate of DDR mode is twice that of SDR mode.…”
Section: Circuit Design Of Acquisition Systemmentioning
confidence: 99%
“…The LTC2325 supports SPI serial interfaces in both CMOS mode and LVDS mode. CMOS mode uses single terminal output for each channel and LVDS mode uses differential output for each channel [8][9]. In SDR mode, data is transmitted at the rising edge of the signal, while in DDR mode, data can be transmitted at both the rising and falling edge of the signal, so the data transmission rate of DDR mode is twice that of SDR mode.…”
Section: Circuit Design Of Acquisition Systemmentioning
confidence: 99%