No abstract

In this study, germanium nanowire junctionless (GeNW-JL) metal-oxide-semiconductor-field-effect-transistors (MOSFETs) exhibited enhanced electrical performance with low source/drain (S/D) contact resistance under the influence of Ar plasma treatment on the contact regions. We found that the transformation of the surface oxide states by Ar plasma treatment affected the S/D contact resistance. With Ar plasma treatment, the germanium dioxide on the GeNW surface was effectively removed and increased oxygen vacancies were formed in the suboxide on the GeNW, whose germanium-enrichment surface was obtained to form a germanide contact at low temperature. After a rapid thermal annealing process, Ni-germanide contacts were formed on the Ar-plasma-treated GeNW surface. Ni-germanide contact resistance was improved by more than an order of magnitude compared to that of the other devices without Ni-germanide contact. Moreover, the peak field effect mobility value of the GeNW-JL MOSFETs was dramatically improved from 15 cm(2)/(V s) to 550 cm(2)/(V s), and the Ion/off ratio was enhanced from 1 × 10 to 3 × 10(3) due to Ar plasma treatment. The Ar plasma treatment process is essential for forming uniform Ni-germanide-contacts with reduced time and low temperature. It is also crucial for increasing mass productivity and lowering the thermal budget without sacrificing the performance of GeNW-JL MOSFETs.

This paper reports the results of the high-rate dry etching of indium gallium zinc oxide (IGZO) at room temperature using BCl3/O2 plasma. We achieved an etch rate of 250 nm/min. We inferred from the x-ray photoelectron spectroscopy analysis that BOx or BOClx radicals generated from BCl3/O2 plasma cause the etching of the IGZO material. O2 initiates the etching of IGZO, and Ar removes nonvolatile byproducts from the surface during the etching process. Consequently, a smooth etched surface results when these gases are added to the etch gas.

No abstract

A germanium tunnel field-effect transistor (TFET) with a bias-induced electron-hole bilayer (EHB) with double gates that are symmetrically arranged and independently biased is simulated. The symmetric double gate scheme is feasible, presenting a simple EHB-TFET structure that is practicable for industrial fabrication. According to simulation results, the improvement of on/off current ratio of ∼10 8 is achieved by inserting a lightly-doped drain-source (LDD) region. Also, fin-type EHB-TFETs show an extremely low average sub-threshold swing of 11 mV/decade over 4 decades at V DD = 0.5 V, and thus are suitable for ultra-low power applications.