First Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation

Kim, Tae Kyun; Kim, Dong Hyun; Yoon, Young Gwang; Moon, Jung Min; Hwang, Byeong Woon; Moon, Dong‐Il; Lee, Gi Seong; Lee, Dong Hoon; Yoo, Dong Eun; Hwang, Hae Chul; Kim, Jin-Soo; Choi, Yang‐Kyu; Cho, Byung Jin; Lee, Seok-Hee

doi:10.1109/led.2013.2283291

Cited by 76 publications

(25 citation statements)

References 16 publications

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“…Further, in both [12] and [13], the analysis is limited to a channel length >60 nm making the BTBT-induced parasitic BJT ineffective due to the larger base width and hence, a lower current gain of the parasitic BJT [3]. As a result, the effect of the BTBTinduced parasitic BJT action in the OFF-state was not studied in [12] or [13]. However, for JLFETs with very short channel lengths (<20 nm), the impact of the BTBT-induced parasitic BJT action becomes very significant [3].…”

Section: Introductionmentioning

confidence: 97%

“…Moreover, this BTBT-induced parasitic BJT action is more pronounced for JLFETs with smaller channel lengths posing serious challenges to the JLFET scaling in the sub-10-nm regime [3]. Recently, a combination of a doped p-type layer over a doped n-type substrate (or vice versa) in the channel region has been experimentally demonstrated in [12] and [13]. The hybrid channel is used to achieve a lesser effective channel thickness and therefore, better gate controllability over the channel region.…”

Section: Introductionmentioning

confidence: 99%

“…The hybrid channel is used to achieve a lesser effective channel thickness and therefore, better gate controllability over the channel region. Further, in both [12] and [13], the analysis is limited to a channel length >60 nm making the BTBT-induced parasitic BJT ineffective due to the larger base width and hence, a lower current gain of the parasitic BJT [3]. As a result, the effect of the BTBTinduced parasitic BJT action in the OFF-state was not studied in [12] or [13].…”

Section: Introductionmentioning

confidence: 99%

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Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

Kumar

Sahay

2016

IEEE Trans. Electron Devices

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In this brief, we demonstrate for the first time that the presence of a hybrid channel, which consists of a p + layer below the n + active device layer in a junctionless (JL) FET, leads to a drastically reduced BTBT-induced parasitic BJT action. Using calibrated 2-D simulations, we show that the JLFET with a p + layer [which we call hole sink (HS)] has a significantly low OFF-state leakage current due to an increased tunneling barrier width, an enhanced source-to-channel barrier height, and a better provision for collecting the band-to-band tunneling (BTBT) generated holes, which results in a diminished parasitic BJT action in the OFF-state. Further, the proposed HS JLFET shows an extremely high ON-state to OFF-state current (I ON /I OFF ) ratio of ∼10 7 for a channel length of 10 nm and a significant (I ON /I OFF ) ratio of ∼10 4 even for a channel length of 5 nm.Index Terms-Band to band tunneling (BTBT), hole sink (HS), junctionless transistor (JLFET), leakage current, parasitic bipolar junction transistor (BJT).

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Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

Kumar

Sahay

2016

IEEE Trans. Electron Devices

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“…The problem of fabrication complexity has been relaxed with JLTs, but they still suffer from lower on‐state current ( V GS = V DS = 1.0 V) due to large series resistances of source and drain extensions ( N D = N S = 10 19 /cm −3 ). Thus, to maximise the on‐state current, junctionless accumulation mode field‐effect transistor (JAMFET) was proposed, which has highly doped source and drain extensions ( N S = N D = 10 20 /cm −3 ) and lightly doped channel region [8, 9]. The presence of highly doped extensions considerably reduce the series resistance and the lightly doped channel region provides higher mobility leading to higher on current in JAMFET as compared with JLT.…”

Section: Introductionmentioning

confidence: 99%

Design approach to improve the performance of JAMFETs

Raushan

Alam

Siddiqui

2020

IET Circuits, Devices & Systems

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In this paper, the authors propose the use of electrostatic doping for n + drain region formation in Junctionless accumulation mode field effect transistors (JAMFET). This electrostatically doped drain (EDD) JAMFET employs an additional unbiased electrode (auxiliary electrode) of low workfunction on the intrinsic drain region. This technique effectively suppresses the tunneling leakage, thereby reducing I OFF by 6 orders. The tunneling of electrons from valence band of channel to conduction band of drain happens due to enhanced band bending in OFF-state (V GS = 0 V, V DS = 1 V). The presence of additional electrode in EDD-JAMFET increases the width of tunnel barrier formed at channel-drain junction in OFF-state improving the I ON /I OFF ratio by 6 orders. The gate length scaling demonstrates that leakage suppression of EDD-JAMFET is more effective with approximately 3 orders smaller I OFF even at gate length of 5 nm. The performance of graded channel device (GC-EDD-JAMFET) by electrostatic doping is also explored. Significant improvements are observed in terms of I ON /I OFF , subthreshold slope SS, DIBL and f T. Finally, the analogue parameters such as Transconductance generation factor G m /I D , Intrinsic gain A V , output conductance G D , and 'G m /I D × f T ' performance metrics are investigated which show significant improvement at small bias current, making it suitable for ultra-low power applications.

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“…JL FET was studied by many researchers [8][9][10] as a promising candidate for highly-scaled devices. Due to the fact that there is no junction in the JL devices, the cost of manufacturing of the device can be reduced.…”

Section: Introductionmentioning

confidence: 99%

Spacer engineering for performance enhancement of junctionless accumulation‐mode bulk FinFETs

Biswas¹,

Sarkar

2017

IET Circuits, Devices & Systems

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This study investigates the performance of the junctionless accumulation-mode (JAM) bulk FinFETs. Different electrical parameters are simulated and analysed for the device with different gate spacer's lengths and materials. Spacers having dielectric constants between 1 and 22 are used to compare the device performance, whereas different spacer lengths are considered in order to understand the effect of spacer engineering. Importance is given to investigate the analogue and radio frequency (RF) performances by computing transconductance (g m), transconductance generation factor (g m /I d), cutoff frequency (f T), maximum frequency of oscillation (f max) and so on. T h ed e v i c eu n d e rs t u d ys h o w sb e t t e rO N-OFF current ratio, transconductance, transconductance generation factor using gate spacer having high k-value. However, because of increased gate capacitances, its RF performance degrades with increase in dielectric constant of the spacer used. The effects of downscaling of channel length (L) on analogue performance of the proposed junctionless accumulation mode device have also been presented. It has been observed that the analogue/RF performance of the device can be improved by reducing the spacer length.

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First Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation

Cited by 76 publications

References 16 publications

Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

Design approach to improve the performance of JAMFETs

Spacer engineering for performance enhancement of junctionless accumulation‐mode bulk FinFETs

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